[PATCH] D106816: [AArch64][GlobalISel] Add identity combines to post-legal combiner.

[Amara Emerson via Phabricator via llvm-commits]

aemerson created this revision.
aemerson added reviewers: paquette, jroelofs.
aemerson added a project: LLVM.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls, rovka.
aemerson requested review of this revision.

We see some shifts of zero emitted during legalization.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D106816

Files:
  llvm/lib/Target/AArch64/AArch64Combine.td
  llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
  llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-identity.mir


Index: llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-identity.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-identity.mir
@@ -0,0 +1,24 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name:            shift_of_zero
+alignment:       4
+legalized:       true
+liveins:
+  - { reg: '$w0' }
+body:             |
+  bb.1.entry:
+    liveins: $x0
+
+    ; CHECK-LABEL: name: shift_of_zero
+    ; CHECK: %a:_(s64) = G_CONSTANT i64 40
+    ; CHECK: $x0 = COPY %a(s64)
+    ; CHECK: RET_ReallyLR implicit $x0
+    %a:_(s64) = G_CONSTANT i64 40
+    %b:_(s64) = G_CONSTANT i64 0
+    %res:_(s64) = G_LSHR %a, %b
+    $x0 = COPY %res(s64)
+    RET_ReallyLR implicit $x0
+
+...
Index: llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
+++ llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
@@ -350,10 +350,8 @@
 ; CHECK-LLSC-O1-NEXT:  .LBB4_1: // %atomicrmw.start
 ; CHECK-LLSC-O1-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECK-LLSC-O1-NEXT:    ldxp x9, x8, [x2]
-; CHECK-LLSC-O1-NEXT:    lsr x8, x8, #0
-; CHECK-LLSC-O1-NEXT:    lsr x10, x8, #0
-; CHECK-LLSC-O1-NEXT:    stxp w11, x9, x10, [x2]
-; CHECK-LLSC-O1-NEXT:    cbnz w11, .LBB4_1
+; CHECK-LLSC-O1-NEXT:    stxp w10, x9, x8, [x2]
+; CHECK-LLSC-O1-NEXT:    cbnz w10, .LBB4_1
 ; CHECK-LLSC-O1-NEXT:  // %bb.2: // %atomicrmw.end
 ; CHECK-LLSC-O1-NEXT:    mov v0.d[0], x9
 ; CHECK-LLSC-O1-NEXT:    mov v0.d[1], x8
@@ -365,10 +363,8 @@
 ; CHECK-CAS-O1-NEXT:  .LBB4_1: // %atomicrmw.start
 ; CHECK-CAS-O1-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECK-CAS-O1-NEXT:    ldxp x9, x8, [x2]
-; CHECK-CAS-O1-NEXT:    lsr x8, x8, #0
-; CHECK-CAS-O1-NEXT:    lsr x10, x8, #0
-; CHECK-CAS-O1-NEXT:    stxp w11, x9, x10, [x2]
-; CHECK-CAS-O1-NEXT:    cbnz w11, .LBB4_1
+; CHECK-CAS-O1-NEXT:    stxp w10, x9, x8, [x2]
+; CHECK-CAS-O1-NEXT:    cbnz w10, .LBB4_1
 ; CHECK-CAS-O1-NEXT:  // %bb.2: // %atomicrmw.end
 ; CHECK-CAS-O1-NEXT:    mov v0.d[0], x9
 ; CHECK-CAS-O1-NEXT:    mov v0.d[1], x8
Index: llvm/lib/Target/AArch64/AArch64Combine.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64Combine.td
+++ llvm/lib/Target/AArch64/AArch64Combine.td
@@ -212,6 +212,6 @@
                         form_bitfield_extract, rotate_out_of_range,
                         icmp_to_true_false_known_bits, merge_unmerge,
                         select_combines, fold_merge_to_zext,
-                        constant_fold]> {
+                        constant_fold, identity_combines]> {
   let DisableRuleOption = "aarch64postlegalizercombiner-disable-rule";
 }


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