[PATCH] D106744: [SVE] Use reg+reg addressing mode for immediate offsets.

[Paul Walker via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG3b77e2737c85: [SVE] Use reg+reg addressing mode for immediate offsets. (authored by paulwalker-arm).

Changed prior to commit:
  https://reviews.llvm.org/D106744?vs=361449&id=361674#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106744/new/

https://reviews.llvm.org/D106744

Files:
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-bit-counting.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-float-compares.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-arith.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-minmax.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-rounding.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-compares.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-minmax.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-reduce.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-shifts.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-loads.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-rev.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-splat-vector.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-stores.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-ld1ro-addressing-mode-reg-imm.ll
  llvm/test/CodeGen/AArch64/sve-vscale-attr.ll

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