[PATCH] D106561: [AArch64] Optimise min/max lowering in ISel
Irina Dobrescu via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 26 08:06:59 PDT 2021
Rin added inline comments.
================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:7108
+ if ((VT != MVT::v1i64 && VT != MVT::v2i64) ||
+ useSVEForFixedLengthVectorVT(VT, /*OverrideNEON=*/true)) {
+ switch (Opcode) {
----------------
david-arm wrote:
> david-arm wrote:
> > I think you might be able to just do this:
> >
> > if (useSVEForFixedLengthVectorVT(VT, /*OverrideNEON=*/true)) {
> >
> > instead?
> Hi @Rin, apologies please ignore my previous comment about changing the if statement. I see now we also want scalable vector types to fall into the block too!
No worries :)
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D106561/new/
https://reviews.llvm.org/D106561
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