[PATCH] D103230: [AMDGPU] Disable NSA for BVH instructions when appropriate

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp:4812
+    // Build a single vector containing all the operands so far prepared.
+    const unsigned LaneCount = NumVAddrs <= 8 ? 8 : 16;
+
----------------
Why do we have to round up to 8 or 16?


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp:4816
+      Register R = MRI.createGenericVirtualRegister(S32);
+      B.buildConstant(R, 0);
+      Ops.push_back(R);
----------------
Can this be undef instead of 0? Can we push the same register N times instead of creating N different registers?


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp:4259
+      // Sequential form: all operands combined into VGPR256/VGPR512
+      OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 512);
+    } else {
----------------
Why does this hard code 512, when the comment says 256 or 512?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103230/new/

https://reviews.llvm.org/D103230