[PATCH] D105575: [AArch64][SME] Add zero instruction

[David Sherwood via Phabricator via llvm-commits]

david-arm accepted this revision.
david-arm added a comment.
This revision is now accepted and ready to land.

LGTM! Thanks for dealing with all the comments @c-rhodes!



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Comment at: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp:2284
+    for (unsigned I = MaxBits; I > 0; --I)
+      OS << ((RegMask & (1 << (I - 1))) >> (I - 1));
+    break;
----------------
c-rhodes wrote:
> david-arm wrote:
> > Do we need a separator here, like ' '?
> > Do we need a separator here, like ' '?
> 
> I don't think so, this just emits the bits, e.g.
> 
> `zero    {za0.s, za2.s} -> <matrixlist 01010101`
> 
> although I realise now the closing `>` is missing, I'll fix that.
nit: I think it's still missing a closing '>'


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105575/new/

https://reviews.llvm.org/D105575