[llvm] 683b9ed - [AMDGPU] Pre-commit global-isel test case for D106451

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2021-07-26T14:27:30+01:00
New Revision: 683b9ed0d593f249e992bed63768986b37b49dbb

URL: https://github.com/llvm/llvm-project/commit/683b9ed0d593f249e992bed63768986b37b49dbb
DIFF: https://github.com/llvm/llvm-project/commit/683b9ed0d593f249e992bed63768986b37b49dbb.diff

LOG: [AMDGPU] Pre-commit global-isel test case for D106451

This test case shows the scheduler wrongly reordering two buffer
accesses that might alias.

Added: 
    llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-schedule.ll

Modified: 
    

Removed: 
    


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diff  --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-schedule.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-schedule.ll
new file mode 100644
index 0000000000000..cbfb47dbdee0d
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-schedule.ll
@@ -0,0 +1,22 @@
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s
+
+; FIXME: the first load and store should not be reordered because they might
+; alias depending on the value of %off
+; GCN-LABEL: {{^}}test1:
+; GCN: buffer_load_dword
+; GCN: buffer_store_dword
+; GCN: buffer_store_dword
+define amdgpu_cs void @test1(<4 x i32> inreg %buf, i32 %off) {
+.entry:
+  call void @llvm.amdgcn.raw.buffer.store.i32(i32 0, <4 x i32> %buf, i32 8, i32 0, i32 0)
+  %val = call i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32> %buf, i32 %off, i32 0, i32 0)
+  call void @llvm.amdgcn.raw.buffer.store.i32(i32 %val, <4 x i32> %buf, i32 0, i32 0, i32 0)
+  ret void
+}
+
+declare i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32>, i32, i32, i32) #2
+
+declare void @llvm.amdgcn.raw.buffer.store.i32(i32, <4 x i32>, i32, i32, i32) #3
+
+attributes #2 = { nounwind readonly }
+attributes #3 = { nounwind writeonly }