[PATCH] D105871: Followup to D99355: implementation of sdag support for vp load/store/gather/scatter.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added a comment.

In D105871#2873713 <https://reviews.llvm.org/D105871#2873713>, @simoll wrote:

> The existing masked/gather/scatter SDNodes have seen some changes since the VP nodes were basically forked from them. I am not familiar with the indexing in masked load, for example. Maybe some of the RISC-V V folks can chime in whether any of the recent masked-sdnode updates should be applied to the vp nodes too.

I feel that it would be best if the SDNodes matched the non-VP ones as closely as possible. RISC-V doesn't have use for `ISD::MemIndexedMode` but some target may have one. I'm thinking even expanding loads and truncating stores should be an option. The only complexity is having to legalize it, but we can hopefully piggy-back on the logic for non-VP nodes.


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