[PATCH] D106408: Allow rematerialization of virtual reg uses

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

In D106408#2897997 <https://reviews.llvm.org/D106408#2897997>, @rampitec wrote:

> @arsenm note, we are reporting that instructions with such uses are trivially materializable for a long time in case of VALU moves, and now even with more VALU instructions. We only do not so it for SALU. I think we will need to have the same check for AllowVRegs in our `isReallyTriviallyReMaterializable` to prevent LICM hoisting it under high pressure.

Although that is practically unexploitable because MachineLICM always thinks there is no high pressure, whatever SALU I feed it from out target, and because `MachineLoop::isLoopInvariant()` always returns false for any VALU because of the exec use. So it always hoists SALU, no matter what, and never hoists VALU. I.e. on practice this change should not pessimize our codegen, because it will not affect LICM for us.


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https://reviews.llvm.org/D106408