[PATCH] D106408: Allow rematerialization of virtual reg uses

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec updated this revision to Diff 360960.
rampitec marked 2 inline comments as done.
rampitec edited the summary of this revision.
rampitec added a comment.
Herald added a subscriber: MatzeB.

Added argument to isTriviallyReMaterializable() to prevent hoisting of instructions in an expectation these can be later rematerialized. Only opportunistic rematerialization in RA is allowed.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106408/new/

https://reviews.llvm.org/D106408

Files:
  llvm/include/llvm/CodeGen/TargetInstrInfo.h
  llvm/lib/CodeGen/CalcSpillWeights.cpp
  llvm/lib/CodeGen/LiveRangeEdit.cpp
  llvm/lib/CodeGen/RegisterCoalescer.cpp
  llvm/lib/CodeGen/TargetInstrInfo.cpp
  llvm/test/CodeGen/AMDGPU/remat-sop.mir
  llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll
  llvm/test/CodeGen/ARM/funnel-shift-rot.ll
  llvm/test/CodeGen/ARM/funnel-shift.ll
  llvm/test/CodeGen/ARM/illegal-bitfield-loadstore.ll
  llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
  llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
  llvm/test/CodeGen/Mips/llvm-ir/shl.ll
  llvm/test/CodeGen/Mips/llvm-ir/sub.ll
  llvm/test/CodeGen/Mips/tls.ll
  llvm/test/CodeGen/RISCV/atomic-rmw.ll
  llvm/test/CodeGen/RISCV/atomic-signext.ll
  llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
  llvm/test/CodeGen/RISCV/rv32i-rv64i-half.ll
  llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
  llvm/test/CodeGen/RISCV/rv32zbb.ll
  llvm/test/CodeGen/RISCV/rv32zbp.ll
  llvm/test/CodeGen/RISCV/rv32zbt.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
  llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
  llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
  llvm/test/CodeGen/Thumb/dyn-stackalloc.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-disabled-in-loloops.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/varying-outer-2d-reduction.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-loops.ll
  llvm/test/CodeGen/Thumb2/ldr-str-imm12.ll
  llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
  llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
  llvm/test/CodeGen/Thumb2/mve-postinc-dct.ll
  llvm/test/CodeGen/X86/addcarry.ll
  llvm/test/CodeGen/X86/callbr-asm-blockplacement.ll
  llvm/test/CodeGen/X86/dag-update-nodetomatch.ll
  llvm/test/CodeGen/X86/inalloca-invoke.ll
  llvm/test/CodeGen/X86/licm-regpressure.ll
  llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
  llvm/test/CodeGen/X86/sdiv_fix.ll

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