[PATCH] D106408: Allow rematerialization of virtual reg uses

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec created this revision.
rampitec added reviewers: arsenm, dstuttard, kparzysz, qcolombet, RKSimon, atanasyan, craig.topper, bevinh.
Herald added subscribers: frasercrmck, kerbowa, luismarques, apazos, sameer.abuasal, pengfei, s.egerton, dmgreen, Jim, asbirlea, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya, kristof.beyls, arichardson, tpr, nhaehnle, jvesely, sdardis.
rampitec requested review of this revision.
Herald added subscribers: MaskRay, wdng.
Herald added a project: LLVM.

Currently isReallyTriviallyReMaterializableGeneric() implementation
prevents rematerialization on any virtual register use on the grounds
that is not a trivial rematerialization and that we do not want to
extend liveranges.

It appears that LRE logic does not attempt to extend a liverange of
a source register for rematerialization so that is not an issue.
That is checked in the LiveRangeEdit::allUsesAvailableAt().

The only non-trivial aspect of it is accounting for tied-defs which
normally represent a read-modify-write operation and not rematerializable.

The test for a tied-def situation already exists in the
/CodeGen/AMDGPU/remat-vop.mir,
test_no_remat_v_cvt_f32_i32_sdwa_dst_unused_preserve.

The change has affected AArch64, ARM/Thumb, Mips, RISCV, and x86.
For the targets where I more or less understand the asm it seems to
reduce spilling (as expected) or be neutral. However, it needs a
review by all targets' specialists.


https://reviews.llvm.org/D106408

Files:
  llvm/lib/CodeGen/TargetInstrInfo.cpp
  llvm/test/CodeGen/AArch64/cmpxchg-idioms.ll
  llvm/test/CodeGen/AMDGPU/remat-sop.mir
  llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll
  llvm/test/CodeGen/ARM/funnel-shift-rot.ll
  llvm/test/CodeGen/ARM/funnel-shift.ll
  llvm/test/CodeGen/ARM/illegal-bitfield-loadstore.ll
  llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
  llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
  llvm/test/CodeGen/Mips/llvm-ir/shl.ll
  llvm/test/CodeGen/Mips/llvm-ir/sub.ll
  llvm/test/CodeGen/Mips/tls.ll
  llvm/test/CodeGen/RISCV/atomic-rmw.ll
  llvm/test/CodeGen/RISCV/atomic-signext.ll
  llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
  llvm/test/CodeGen/RISCV/rv32i-rv64i-half.ll
  llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
  llvm/test/CodeGen/RISCV/rv32zbb.ll
  llvm/test/CodeGen/RISCV/rv32zbp.ll
  llvm/test/CodeGen/RISCV/rv32zbt.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
  llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
  llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
  llvm/test/CodeGen/Thumb/dyn-stackalloc.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/memcall.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-disabled-in-loloops.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/varying-outer-2d-reduction.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-loops.ll
  llvm/test/CodeGen/Thumb2/ldr-str-imm12.ll
  llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
  llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
  llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll
  llvm/test/CodeGen/Thumb2/mve-memtp-loop.ll
  llvm/test/CodeGen/Thumb2/mve-postinc-dct.ll
  llvm/test/CodeGen/X86/addcarry.ll
  llvm/test/CodeGen/X86/callbr-asm-blockplacement.ll
  llvm/test/CodeGen/X86/dag-update-nodetomatch.ll
  llvm/test/CodeGen/X86/inalloca-invoke.ll
  llvm/test/CodeGen/X86/licm-regpressure.ll
  llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
  llvm/test/CodeGen/X86/sdiv_fix.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D106408.360302.patch
Type: text/x-patch
Size: 455630 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210720/3ad98ea6/attachment-0001.bin>