[PATCH] D106679: [WIP][X86] Move shl(x, 1) -> add(x, x) vector fold to ISEL (PR50468)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
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Partial alternative to D106675 <https://reviews.llvm.org/D106675> to avoid the undef issues identified in PR50468 by using alternative isel patterns for vXi16/vXi32/vXi64 shl-by-one.

This affects many cases which weren't being picked up in time by combineShiftLeft() - which since this is a performance combine is probably a good thing - plus it avoids some HasOneUse issues that allows some additional optimization.

The vXi8 shl-by-one would still need to be performed using FREEZE - I don't know if anyone has concerns about having different methods?


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D106679

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86InstrAVX512.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/test/CodeGen/X86/combine-mul.ll
  llvm/test/CodeGen/X86/combine-sdiv.ll
  llvm/test/CodeGen/X86/lower-vec-shift.ll
  llvm/test/CodeGen/X86/oddsubvector.ll
  llvm/test/CodeGen/X86/sdiv_fix_sat.ll
  llvm/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll
  llvm/test/CodeGen/X86/stack-folding-int-avx512.ll
  llvm/test/CodeGen/X86/udiv_fix_sat.ll
  llvm/test/CodeGen/X86/vec_shift6.ll
  llvm/test/CodeGen/X86/vector-fshr-128.ll
  llvm/test/CodeGen/X86/vector-fshr-256.ll
  llvm/test/CodeGen/X86/vector-fshr-512.ll
  llvm/test/CodeGen/X86/vector-mulfix-legalize.ll
  llvm/test/CodeGen/X86/vector-shift-shl-128.ll
  llvm/test/CodeGen/X86/vector-shift-shl-256.ll
  llvm/test/CodeGen/X86/widen_arith-4.ll

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