[PATCH] D106675: [WIP][X86] Freeze shl(x,1) -> add(x,x) vector fold (PR50468)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: craig.topper, spatel, pengfei.
Herald added a subscriber: hiraditya.
RKSimon requested review of this revision.
Herald added a project: LLVM.

Demo patch to show the effect of folding shl(x,1) ->add(freeze(x),freeze(x)) to avoid the undef issues identified in PR50468

I have a second patch that adds alternative isel patterns for vXi16/vXi32/vXi64 shl-by-one - I'll raise that for comparison shortly.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D106675

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/bitreverse.ll
  llvm/test/CodeGen/X86/combine-bitreverse.ll
  llvm/test/CodeGen/X86/oddsubvector.ll
  llvm/test/CodeGen/X86/sdiv_fix_sat.ll
  llvm/test/CodeGen/X86/vector-bitreverse.ll
  llvm/test/CodeGen/X86/vector-fshl-rot-128.ll
  llvm/test/CodeGen/X86/vector-fshl-rot-256.ll
  llvm/test/CodeGen/X86/vector-fshl-rot-512.ll
  llvm/test/CodeGen/X86/vector-fshr-128.ll
  llvm/test/CodeGen/X86/vector-fshr-256.ll
  llvm/test/CodeGen/X86/vector-fshr-rot-128.ll
  llvm/test/CodeGen/X86/vector-fshr-rot-256.ll
  llvm/test/CodeGen/X86/vector-fshr-rot-512.ll
  llvm/test/CodeGen/X86/vector-gep.ll
  llvm/test/CodeGen/X86/vector-rotate-128.ll
  llvm/test/CodeGen/X86/vector-rotate-256.ll

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