[PATCH] D105709: [AMDGPU][GlobalISel] Insert an and with exec before s_cbranch_vccnz if necessary
Mirko Brkusanin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 23 08:13:51 PDT 2021
mbrkusanin added inline comments.
================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp:2496
+ const unsigned CondDefOpc = MRI->getUniqueVRegDef(CondReg)->getOpcode();
+ if (CondDefOpc != AMDGPU::G_ICMP && CondDefOpc != AMDGPU::G_FCMP) {
+ const bool Is64 = STI.isWave64();
----------------
arsenm wrote:
> foad wrote:
> > arsenm wrote:
> > > This isn't the precise condition. It should also cover class intrinsics and maybe a few other cases. I thought we had an is known vector bool helper somewhere?
> > >
> > For SelectionDAG we have isBoolSGPR. I don't know of anything similar for GlobalISel.
> We should have the equivalent
I could not find a global-isel equivalent.
================
Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir:231-233
+ %2:sgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.icmp), %0:vgpr(s64), %1:vgpr(s64), 32
+ %3:sgpr(s1) = G_TRUNC %2
+ %4:vcc(s1) = COPY %3
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Is this correct? As far as I can tell this is the only way to copy sgpr to vcc.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D105709/new/
https://reviews.llvm.org/D105709
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