[PATCH] D106666: [PowerPC]Add addex instruction definition and MC tests

[Lei Huang via Phabricator via llvm-commits]

lei created this revision.
lei added reviewers: nemanjai, amyk, NeHuang, power-llvm-team.
Herald added subscribers: shchenz, hiraditya.
lei requested review of this revision.
Herald added a project: LLVM.

Add td definitions and asm/disasm tests for the addex instruction introduced in
ISA 3.0.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D106666

Files:
  llvm/lib/Target/PowerPC/P9InstrResources.td
  llvm/lib/Target/PowerPC/PPCInstrFormats.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
  llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt
  llvm/test/MC/PowerPC/ppc64-encoding.s


Index: llvm/test/MC/PowerPC/ppc64-encoding.s
===================================================================
--- llvm/test/MC/PowerPC/ppc64-encoding.s
+++ llvm/test/MC/PowerPC/ppc64-encoding.s
@@ -416,6 +416,9 @@
 # CHECK-BE: addeo. 2, 3, 4                  # encoding: [0x7c,0x43,0x25,0x15]
 # CHECK-LE: addeo. 2, 3, 4                  # encoding: [0x15,0x25,0x43,0x7c]
             addeo. 2, 3, 4
+# CHECK-BE: addex 2, 4, 5, 0                # encoding: [0x7c,0x44,0x29,0x54]
+# CHECK-LE: addex 2, 4, 5, 0                # encoding: [0x54,0x29,0x44,0x7c]
+            addex 2, 4, 5, 0
 # CHECK-BE: subfe 2, 3, 4                   # encoding: [0x7c,0x43,0x21,0x10]
 # CHECK-LE: subfe 2, 3, 4                   # encoding: [0x10,0x21,0x43,0x7c]
             subfe 2, 3, 4
Index: llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt
===================================================================
--- llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt
+++ llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt
@@ -448,6 +448,9 @@
 # CHECK: modsw 2, 3, 4
 0x16 0x26 0x43 0x7c
 
+# CHECK: addex 2, 4, 5, 0
+0x54 0x29 0x44 0x7C
+
 # CHECK: moduw 2, 3, 4
 0x16 0x22 0x43 0x7c
 
Index: llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
===================================================================
--- llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
+++ llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
@@ -484,6 +484,9 @@
 # CHECK: modsw 2, 3, 4
 0x7c 0x43 0x26 0x16
 
+# CHECK: addex 2, 4, 5, 0
+0x7C 0x44 0x29 0x54
+
 # CHECK: moduw 2, 3, 4
 0x7c 0x43 0x22 0x16
 
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -3155,6 +3155,10 @@
 def MODUW : XForm_8<31, 267, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
                         "moduw $rT, $rA, $rB", IIC_IntDivW,
                         [(set i32:$rT, (urem i32:$rA, i32:$rB))]>;
+let hasSideEffects = 1 in
+def ADDEX : Z23Form_RTAB5_CY2<31, 170, (outs gprc:$rT),
+                              (ins gprc:$rA, gprc:$rB, u2imm:$CY),
+                              "addex $rT, $rA, $rB, $CY", IIC_IntGeneral, []>;
 }
 
 let PPC970_Unit = 1, hasSideEffects = 0 in {  // FXU Operations.
Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrFormats.td
+++ llvm/lib/Target/PowerPC/PPCInstrFormats.td
@@ -2141,6 +2141,25 @@
   let Inst{31}    = RC;
 }
 
+class Z23Form_RTAB5_CY2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
+                        string asmstr, InstrItinClass itin, list<dag> pattern>
+         : I<opcode, OOL, IOL, asmstr, itin> {
+  bits<5> RT;
+  bits<5> RA;
+  bits<5> RB;
+  bits<2> CY;
+
+  let Pattern = pattern;
+
+  let Inst{6-10}  = RT;
+  let Inst{11-15} = RA;
+  let Inst{16-20} = RB;
+  let Inst{21-22} = CY;
+  let Inst{23-30} = xo;
+  let Inst{31} = 0;
+}
+
+
 //===----------------------------------------------------------------------===//
 // EmitTimePseudo won't have encoding information for the [MC]CodeEmitter
 // stuff
Index: llvm/lib/Target/PowerPC/P9InstrResources.td
===================================================================
--- llvm/lib/Target/PowerPC/P9InstrResources.td
+++ llvm/lib/Target/PowerPC/P9InstrResources.td
@@ -1429,5 +1429,6 @@
   DCBA,
   DCBI,
   DCCCI,
-  ICCCI
+  ICCCI,
+  ADDEX
 )> { let Unsupported = 1; }


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