[PATCH] D106633: [RISCV][Docs] Add description about inline asm constraint for V.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


================
Comment at: llvm/docs/LangRef.rst:4770
   ``XLEN``).
+- ``v``: A vector register. Clang uses ``vr`` for vector registers and ``vm``
+  for vector mask registers. (requires V extension).
----------------
kito-cheng wrote:
> I thought we only support `vr` and `vm`, but `v` only is not supported?
In LLVM IR, it still keeps to only use 'v'. The document is IR document. That's why I describe 'v' here.

In Clang, it will convert 'vr' and 'vm' to 'v' in LLVM IR.

You could see the `convertConstraint` in https://reviews.llvm.org/D98616.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106633/new/

https://reviews.llvm.org/D106633