[llvm] 424fe90 - [AMDGPU][MC][GFX9][NFC][DOC] Updated AMD GPU assembler syntax description.
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 23 03:29:19 PDT 2021
Author: Dmitry Preobrazhensky
Date: 2021-07-23T12:59:42+03:00
New Revision: 424fe903d4d4b0f52bd4f86f62587efa6561d251
URL: https://github.com/llvm/llvm-project/commit/424fe903d4d4b0f52bd4f86f62587efa6561d251
DIFF: https://github.com/llvm/llvm-project/commit/424fe903d4d4b0f52bd4f86f62587efa6561d251.diff
LOG: [AMDGPU][MC][GFX9][NFC][DOC] Updated AMD GPU assembler syntax description.
Fixed bugs 48639, 49447, 49448, 49449.
Added:
llvm/docs/AMDGPU/gfx9_dst.rst
llvm/docs/AMDGPU/gfx9_imm16.rst
llvm/docs/AMDGPU/gfx9_imm16_1.rst
llvm/docs/AMDGPU/gfx9_imm16_2.rst
llvm/docs/AMDGPU/gfx9_m.rst
llvm/docs/AMDGPU/gfx9_m_1.rst
llvm/docs/AMDGPU/gfx9_probe.rst
llvm/docs/AMDGPU/gfx9_saddr.rst
llvm/docs/AMDGPU/gfx9_saddr_1.rst
llvm/docs/AMDGPU/gfx9_sbase.rst
llvm/docs/AMDGPU/gfx9_sbase_1.rst
llvm/docs/AMDGPU/gfx9_sbase_2.rst
llvm/docs/AMDGPU/gfx9_sdata.rst
llvm/docs/AMDGPU/gfx9_sdata_1.rst
llvm/docs/AMDGPU/gfx9_sdata_2.rst
llvm/docs/AMDGPU/gfx9_sdata_3.rst
llvm/docs/AMDGPU/gfx9_sdata_4.rst
llvm/docs/AMDGPU/gfx9_sdata_5.rst
llvm/docs/AMDGPU/gfx9_sdst.rst
llvm/docs/AMDGPU/gfx9_sdst_1.rst
llvm/docs/AMDGPU/gfx9_sdst_2.rst
llvm/docs/AMDGPU/gfx9_sdst_3.rst
llvm/docs/AMDGPU/gfx9_sdst_4.rst
llvm/docs/AMDGPU/gfx9_sdst_5.rst
llvm/docs/AMDGPU/gfx9_sdst_6.rst
llvm/docs/AMDGPU/gfx9_sdst_7.rst
llvm/docs/AMDGPU/gfx9_simm32.rst
llvm/docs/AMDGPU/gfx9_simm32_1.rst
llvm/docs/AMDGPU/gfx9_simm32_2.rst
llvm/docs/AMDGPU/gfx9_soffset.rst
llvm/docs/AMDGPU/gfx9_soffset_1.rst
llvm/docs/AMDGPU/gfx9_soffset_2.rst
llvm/docs/AMDGPU/gfx9_src.rst
llvm/docs/AMDGPU/gfx9_src_1.rst
llvm/docs/AMDGPU/gfx9_src_10.rst
llvm/docs/AMDGPU/gfx9_src_2.rst
llvm/docs/AMDGPU/gfx9_src_3.rst
llvm/docs/AMDGPU/gfx9_src_4.rst
llvm/docs/AMDGPU/gfx9_src_5.rst
llvm/docs/AMDGPU/gfx9_src_6.rst
llvm/docs/AMDGPU/gfx9_src_7.rst
llvm/docs/AMDGPU/gfx9_src_8.rst
llvm/docs/AMDGPU/gfx9_src_9.rst
llvm/docs/AMDGPU/gfx9_srsrc.rst
llvm/docs/AMDGPU/gfx9_srsrc_1.rst
llvm/docs/AMDGPU/gfx9_ssamp.rst
llvm/docs/AMDGPU/gfx9_ssrc.rst
llvm/docs/AMDGPU/gfx9_ssrc_1.rst
llvm/docs/AMDGPU/gfx9_ssrc_2.rst
llvm/docs/AMDGPU/gfx9_ssrc_3.rst
llvm/docs/AMDGPU/gfx9_ssrc_4.rst
llvm/docs/AMDGPU/gfx9_ssrc_5.rst
llvm/docs/AMDGPU/gfx9_ssrc_6.rst
llvm/docs/AMDGPU/gfx9_ssrc_7.rst
llvm/docs/AMDGPU/gfx9_ssrc_8.rst
llvm/docs/AMDGPU/gfx9_type_deviation.rst
llvm/docs/AMDGPU/gfx9_vaddr.rst
llvm/docs/AMDGPU/gfx9_vaddr_1.rst
llvm/docs/AMDGPU/gfx9_vaddr_2.rst
llvm/docs/AMDGPU/gfx9_vaddr_3.rst
llvm/docs/AMDGPU/gfx9_vaddr_4.rst
llvm/docs/AMDGPU/gfx9_vaddr_5.rst
llvm/docs/AMDGPU/gfx9_vcc.rst
llvm/docs/AMDGPU/gfx9_vdata.rst
llvm/docs/AMDGPU/gfx9_vdata0.rst
llvm/docs/AMDGPU/gfx9_vdata0_1.rst
llvm/docs/AMDGPU/gfx9_vdata1.rst
llvm/docs/AMDGPU/gfx9_vdata1_1.rst
llvm/docs/AMDGPU/gfx9_vdata_1.rst
llvm/docs/AMDGPU/gfx9_vdata_10.rst
llvm/docs/AMDGPU/gfx9_vdata_2.rst
llvm/docs/AMDGPU/gfx9_vdata_3.rst
llvm/docs/AMDGPU/gfx9_vdata_4.rst
llvm/docs/AMDGPU/gfx9_vdata_5.rst
llvm/docs/AMDGPU/gfx9_vdata_6.rst
llvm/docs/AMDGPU/gfx9_vdata_7.rst
llvm/docs/AMDGPU/gfx9_vdata_8.rst
llvm/docs/AMDGPU/gfx9_vdata_9.rst
llvm/docs/AMDGPU/gfx9_vdst.rst
llvm/docs/AMDGPU/gfx9_vdst_1.rst
llvm/docs/AMDGPU/gfx9_vdst_10.rst
llvm/docs/AMDGPU/gfx9_vdst_11.rst
llvm/docs/AMDGPU/gfx9_vdst_12.rst
llvm/docs/AMDGPU/gfx9_vdst_13.rst
llvm/docs/AMDGPU/gfx9_vdst_2.rst
llvm/docs/AMDGPU/gfx9_vdst_3.rst
llvm/docs/AMDGPU/gfx9_vdst_4.rst
llvm/docs/AMDGPU/gfx9_vdst_5.rst
llvm/docs/AMDGPU/gfx9_vdst_6.rst
llvm/docs/AMDGPU/gfx9_vdst_7.rst
llvm/docs/AMDGPU/gfx9_vdst_8.rst
llvm/docs/AMDGPU/gfx9_vdst_9.rst
llvm/docs/AMDGPU/gfx9_vsrc.rst
llvm/docs/AMDGPU/gfx9_vsrc_1.rst
llvm/docs/AMDGPU/gfx9_vsrc_2.rst
llvm/docs/AMDGPU/gfx9_vsrc_3.rst
Modified:
llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst
llvm/docs/AMDGPU/gfx9_attr.rst
llvm/docs/AMDGPU/gfx9_hwreg.rst
llvm/docs/AMDGPU/gfx9_imask.rst
llvm/docs/AMDGPU/gfx9_label.rst
llvm/docs/AMDGPU/gfx9_msg.rst
llvm/docs/AMDGPU/gfx9_opt.rst
llvm/docs/AMDGPU/gfx9_param.rst
llvm/docs/AMDGPU/gfx9_tgt.rst
llvm/docs/AMDGPU/gfx9_waitcnt.rst
Removed:
llvm/docs/AMDGPU/gfx9_addr_buf.rst
llvm/docs/AMDGPU/gfx9_addr_ds.rst
llvm/docs/AMDGPU/gfx9_addr_flat.rst
llvm/docs/AMDGPU/gfx9_addr_mimg.rst
llvm/docs/AMDGPU/gfx9_base_smem_addr.rst
llvm/docs/AMDGPU/gfx9_base_smem_buf.rst
llvm/docs/AMDGPU/gfx9_base_smem_scratch.rst
llvm/docs/AMDGPU/gfx9_bimm16.rst
llvm/docs/AMDGPU/gfx9_bimm32.rst
llvm/docs/AMDGPU/gfx9_data_buf_atomic128.rst
llvm/docs/AMDGPU/gfx9_data_buf_atomic32.rst
llvm/docs/AMDGPU/gfx9_data_buf_atomic64.rst
llvm/docs/AMDGPU/gfx9_data_mimg_atomic_cmp.rst
llvm/docs/AMDGPU/gfx9_data_mimg_atomic_reg.rst
llvm/docs/AMDGPU/gfx9_data_mimg_store.rst
llvm/docs/AMDGPU/gfx9_data_mimg_store_d16.rst
llvm/docs/AMDGPU/gfx9_data_smem_atomic128.rst
llvm/docs/AMDGPU/gfx9_data_smem_atomic32.rst
llvm/docs/AMDGPU/gfx9_data_smem_atomic64.rst
llvm/docs/AMDGPU/gfx9_dst_buf_128.rst
llvm/docs/AMDGPU/gfx9_dst_buf_32.rst
llvm/docs/AMDGPU/gfx9_dst_buf_64.rst
llvm/docs/AMDGPU/gfx9_dst_buf_96.rst
llvm/docs/AMDGPU/gfx9_dst_buf_lds.rst
llvm/docs/AMDGPU/gfx9_dst_flat_atomic32.rst
llvm/docs/AMDGPU/gfx9_dst_flat_atomic64.rst
llvm/docs/AMDGPU/gfx9_dst_mimg_gather4.rst
llvm/docs/AMDGPU/gfx9_dst_mimg_regular.rst
llvm/docs/AMDGPU/gfx9_dst_mimg_regular_d16.rst
llvm/docs/AMDGPU/gfx9_fimm16.rst
llvm/docs/AMDGPU/gfx9_fimm32.rst
llvm/docs/AMDGPU/gfx9_mod_dpp_sdwa_abs_neg.rst
llvm/docs/AMDGPU/gfx9_mod_sdwa_sext.rst
llvm/docs/AMDGPU/gfx9_mod_vop3_abs_neg.rst
llvm/docs/AMDGPU/gfx9_offset_buf.rst
llvm/docs/AMDGPU/gfx9_offset_smem_buf.rst
llvm/docs/AMDGPU/gfx9_offset_smem_plain.rst
llvm/docs/AMDGPU/gfx9_perm_smem.rst
llvm/docs/AMDGPU/gfx9_ret.rst
llvm/docs/AMDGPU/gfx9_rsrc_buf.rst
llvm/docs/AMDGPU/gfx9_rsrc_mimg.rst
llvm/docs/AMDGPU/gfx9_saddr_flat_global.rst
llvm/docs/AMDGPU/gfx9_saddr_flat_scratch.rst
llvm/docs/AMDGPU/gfx9_samp_mimg.rst
llvm/docs/AMDGPU/gfx9_sdata128_0.rst
llvm/docs/AMDGPU/gfx9_sdata32_0.rst
llvm/docs/AMDGPU/gfx9_sdata64_0.rst
llvm/docs/AMDGPU/gfx9_sdst128_0.rst
llvm/docs/AMDGPU/gfx9_sdst256_0.rst
llvm/docs/AMDGPU/gfx9_sdst32_0.rst
llvm/docs/AMDGPU/gfx9_sdst32_1.rst
llvm/docs/AMDGPU/gfx9_sdst32_2.rst
llvm/docs/AMDGPU/gfx9_sdst512_0.rst
llvm/docs/AMDGPU/gfx9_sdst64_0.rst
llvm/docs/AMDGPU/gfx9_sdst64_1.rst
llvm/docs/AMDGPU/gfx9_simm16.rst
llvm/docs/AMDGPU/gfx9_src32_0.rst
llvm/docs/AMDGPU/gfx9_src32_1.rst
llvm/docs/AMDGPU/gfx9_src32_2.rst
llvm/docs/AMDGPU/gfx9_src32_3.rst
llvm/docs/AMDGPU/gfx9_src32_4.rst
llvm/docs/AMDGPU/gfx9_src32_5.rst
llvm/docs/AMDGPU/gfx9_src32_6.rst
llvm/docs/AMDGPU/gfx9_src32_7.rst
llvm/docs/AMDGPU/gfx9_src64_0.rst
llvm/docs/AMDGPU/gfx9_src64_1.rst
llvm/docs/AMDGPU/gfx9_src_exp.rst
llvm/docs/AMDGPU/gfx9_ssrc32_0.rst
llvm/docs/AMDGPU/gfx9_ssrc32_1.rst
llvm/docs/AMDGPU/gfx9_ssrc32_2.rst
llvm/docs/AMDGPU/gfx9_ssrc32_3.rst
llvm/docs/AMDGPU/gfx9_ssrc32_4.rst
llvm/docs/AMDGPU/gfx9_ssrc64_0.rst
llvm/docs/AMDGPU/gfx9_ssrc64_1.rst
llvm/docs/AMDGPU/gfx9_ssrc64_2.rst
llvm/docs/AMDGPU/gfx9_ssrc64_3.rst
llvm/docs/AMDGPU/gfx9_type_dev.rst
llvm/docs/AMDGPU/gfx9_uimm16.rst
llvm/docs/AMDGPU/gfx9_vaddr_flat_global.rst
llvm/docs/AMDGPU/gfx9_vaddr_flat_scratch.rst
llvm/docs/AMDGPU/gfx9_vcc_64.rst
llvm/docs/AMDGPU/gfx9_vdata128_0.rst
llvm/docs/AMDGPU/gfx9_vdata32_0.rst
llvm/docs/AMDGPU/gfx9_vdata64_0.rst
llvm/docs/AMDGPU/gfx9_vdata96_0.rst
llvm/docs/AMDGPU/gfx9_vdst128_0.rst
llvm/docs/AMDGPU/gfx9_vdst32_0.rst
llvm/docs/AMDGPU/gfx9_vdst64_0.rst
llvm/docs/AMDGPU/gfx9_vdst96_0.rst
llvm/docs/AMDGPU/gfx9_vsrc128_0.rst
llvm/docs/AMDGPU/gfx9_vsrc32_0.rst
llvm/docs/AMDGPU/gfx9_vsrc32_1.rst
llvm/docs/AMDGPU/gfx9_vsrc64_0.rst
################################################################################
diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst
index dc8d7e7d2a3a..338b192ac0d6 100644
--- a/llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst
+++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst
@@ -37,161 +37,161 @@ DS
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
- \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- ds_add_f32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_rtn_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_rtn_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_rtn_u64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_src2_f32 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_src2_u32 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_src2_u64 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_u32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_u64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_and_b32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_and_b64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_and_rtn_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_and_rtn_b64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_and_src2_b32 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_and_src2_b64 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_append :ref:`vdst<amdgpu_synid9_vdst32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_bpermute_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>`
- ds_cmpst_b32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata32_0>`, :ref:`vdata1<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_b64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata64_0>`, :ref:`vdata1<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_f32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata32_0>`, :ref:`vdata1<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_f64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata64_0>`, :ref:`vdata1<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_rtn_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata32_0>`, :ref:`vdata1<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_rtn_b64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata64_0>`, :ref:`vdata1<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_rtn_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata32_0>`, :ref:`vdata1<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_rtn_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata64_0>`, :ref:`vdata1<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_condxchg32_rtn_b64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_consume :ref:`vdst<amdgpu_synid9_vdst32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_dec_rtn_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_dec_rtn_u64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_dec_src2_u32 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_dec_src2_u64 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_dec_u32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_dec_u64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_gws_barrier :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_gws_init :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_gws_sema_br :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ ds_add_f32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_rtn_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_rtn_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_rtn_u64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_src2_f32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_src2_u32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_src2_u64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_u32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_u64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_b32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_b64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_rtn_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_rtn_b64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_src2_b32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_src2_b64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_append :ref:`vdst<amdgpu_synid_gfx9_vdst>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_bpermute_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>`
+ ds_cmpst_b32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx9_vdata0>`, :ref:`vdata1<amdgpu_synid_gfx9_vdata1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_b64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx9_vdata0_1>`, :ref:`vdata1<amdgpu_synid_gfx9_vdata1_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_f32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx9_vdata0>`, :ref:`vdata1<amdgpu_synid_gfx9_vdata1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_f64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx9_vdata0_1>`, :ref:`vdata1<amdgpu_synid_gfx9_vdata1_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx9_vdata0>`, :ref:`vdata1<amdgpu_synid_gfx9_vdata1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_b64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx9_vdata0_1>`, :ref:`vdata1<amdgpu_synid_gfx9_vdata1_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx9_vdata0>`, :ref:`vdata1<amdgpu_synid_gfx9_vdata1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_f64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx9_vdata0_1>`, :ref:`vdata1<amdgpu_synid_gfx9_vdata1_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_condxchg32_rtn_b64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_consume :ref:`vdst<amdgpu_synid_gfx9_vdst>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_rtn_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_rtn_u64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_src2_u32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_src2_u64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_u32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_u64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_barrier :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_init :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_sema_br :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_gws_sema_p :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_gws_sema_release_all :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_gws_sema_v :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_inc_rtn_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_inc_rtn_u64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_inc_src2_u32 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_inc_src2_u64 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_inc_u32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_inc_u64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_f32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_f64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_i32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_i64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_rtn_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_rtn_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_rtn_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_rtn_i64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_rtn_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_rtn_u64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_src2_f32 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_src2_f64 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_src2_i32 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_src2_i64 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_src2_u32 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_src2_u64 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_u32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_u64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_f32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_f64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_i32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_i64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_rtn_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_rtn_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_rtn_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_rtn_i64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_rtn_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_rtn_u64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_src2_f32 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_src2_f64 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_src2_i32 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_src2_i64 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_src2_u32 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_src2_u64 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_u32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_u64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_mskor_b32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata32_0>`, :ref:`vdata1<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_mskor_b64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata64_0>`, :ref:`vdata1<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_mskor_rtn_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata32_0>`, :ref:`vdata1<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_mskor_rtn_b64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata64_0>`, :ref:`vdata1<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_rtn_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_rtn_u64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_src2_u32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_src2_u64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_u32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_u64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_f32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_f64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_i32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_i64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_f64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_i32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_i64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_u64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_src2_f32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_src2_f64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_src2_i32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_src2_i64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_src2_u32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_src2_u64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_u32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_u64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_f32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_f64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_i32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_i64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_f64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_i32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_i64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_u64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_src2_f32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_src2_f64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_src2_i32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_src2_i64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_src2_u32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_src2_u64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_u32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_u64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_b32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx9_vdata0>`, :ref:`vdata1<amdgpu_synid_gfx9_vdata1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_b64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx9_vdata0_1>`, :ref:`vdata1<amdgpu_synid_gfx9_vdata1_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_rtn_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx9_vdata0>`, :ref:`vdata1<amdgpu_synid_gfx9_vdata1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_rtn_b64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx9_vdata0_1>`, :ref:`vdata1<amdgpu_synid_gfx9_vdata1_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_nop
- ds_or_b32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_or_b64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_or_rtn_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_or_rtn_b64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_or_src2_b32 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_or_src2_b64 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_ordered_count :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_permute_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>`
- ds_read2_b32 :ref:`vdst<amdgpu_synid9_vdst64_0>`::ref:`b32x2<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_read2_b64 :ref:`vdst<amdgpu_synid9_vdst128_0>`::ref:`b64x2<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_read2st64_b32 :ref:`vdst<amdgpu_synid9_vdst64_0>`::ref:`b32x2<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_read2st64_b64 :ref:`vdst<amdgpu_synid9_vdst128_0>`::ref:`b64x2<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_addtid_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_b128 :ref:`vdst<amdgpu_synid9_vdst128_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_b64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_b96 :ref:`vdst<amdgpu_synid9_vdst96_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_i8 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_i8_d16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_i8_d16_hi :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_u16_d16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_u16_d16_hi :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_u8 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_u8_d16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_u8_d16_hi :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_rsub_rtn_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_rsub_rtn_u64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_rsub_src2_u32 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_rsub_src2_u64 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_rsub_u32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_rsub_u64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_sub_rtn_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_sub_rtn_u64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_sub_src2_u32 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_sub_src2_u64 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_sub_u32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_sub_u64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_swizzle_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`pattern<amdgpu_synid_sw_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_wrap_rtn_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata32_0>`, :ref:`vdata1<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write2_b32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata32_0>`, :ref:`vdata1<amdgpu_synid9_vdata32_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_write2_b64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata64_0>`, :ref:`vdata1<amdgpu_synid9_vdata64_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_write2st64_b32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata32_0>`, :ref:`vdata1<amdgpu_synid9_vdata32_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_write2st64_b64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata64_0>`, :ref:`vdata1<amdgpu_synid9_vdata64_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_addtid_b32 :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_b128 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata128_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_b16 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_b16_d16_hi :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_b32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_b64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_b8 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_b8_d16_hi :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_b96 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata96_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_src2_b32 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_src2_b64 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_wrxchg2_rtn_b32 :ref:`vdst<amdgpu_synid9_vdst64_0>`::ref:`b32x2<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata32_0>`, :ref:`vdata1<amdgpu_synid9_vdata32_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_wrxchg2_rtn_b64 :ref:`vdst<amdgpu_synid9_vdst128_0>`::ref:`b64x2<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata64_0>`, :ref:`vdata1<amdgpu_synid9_vdata64_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_wrxchg2st64_rtn_b32 :ref:`vdst<amdgpu_synid9_vdst64_0>`::ref:`b32x2<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata32_0>`, :ref:`vdata1<amdgpu_synid9_vdata32_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_wrxchg2st64_rtn_b64 :ref:`vdst<amdgpu_synid9_vdst128_0>`::ref:`b64x2<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata64_0>`, :ref:`vdata1<amdgpu_synid9_vdata64_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
- ds_wrxchg_rtn_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_wrxchg_rtn_b64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_xor_b32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_xor_b64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_xor_rtn_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_xor_rtn_b64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_xor_src2_b32 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_xor_src2_b64 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_b32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_b64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_rtn_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_rtn_b64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_src2_b32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_src2_b64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_ordered_count :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_permute_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>`
+ ds_read2_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`::ref:`b32x2<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read2_b64 :ref:`vdst<amdgpu_synid_gfx9_vdst_2>`::ref:`b64x2<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read2st64_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`::ref:`b32x2<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read2st64_b64 :ref:`vdst<amdgpu_synid_gfx9_vdst_2>`::ref:`b64x2<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_addtid_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b128 :ref:`vdst<amdgpu_synid_gfx9_vdst_2>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b96 :ref:`vdst<amdgpu_synid_gfx9_vdst_3>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_i16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_i8 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_i8_d16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_i8_d16_hi :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u16_d16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u16_d16_hi :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u8 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u8_d16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u8_d16_hi :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_rtn_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_rtn_u64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_src2_u32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_src2_u64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_u32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_u64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_rtn_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_rtn_u64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_src2_u32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_src2_u64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_u32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_u64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_swizzle_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`pattern<amdgpu_synid_sw_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrap_rtn_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx9_vdata0>`, :ref:`vdata1<amdgpu_synid_gfx9_vdata1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2_b32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx9_vdata0>`, :ref:`vdata1<amdgpu_synid_gfx9_vdata1>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2_b64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx9_vdata0_1>`, :ref:`vdata1<amdgpu_synid_gfx9_vdata1_1>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2st64_b32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx9_vdata0>`, :ref:`vdata1<amdgpu_synid_gfx9_vdata1>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2st64_b64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx9_vdata0_1>`, :ref:`vdata1<amdgpu_synid_gfx9_vdata1_1>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_addtid_b32 :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b128 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_2>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b16 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b16_d16_hi :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b8 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b8_d16_hi :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b96 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_3>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_src2_b32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_src2_b64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2_rtn_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`::ref:`b32x2<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx9_vdata0>`, :ref:`vdata1<amdgpu_synid_gfx9_vdata1>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2_rtn_b64 :ref:`vdst<amdgpu_synid_gfx9_vdst_2>`::ref:`b64x2<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx9_vdata0_1>`, :ref:`vdata1<amdgpu_synid_gfx9_vdata1_1>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2st64_rtn_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`::ref:`b32x2<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx9_vdata0>`, :ref:`vdata1<amdgpu_synid_gfx9_vdata1>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2st64_rtn_b64 :ref:`vdst<amdgpu_synid_gfx9_vdst_2>`::ref:`b64x2<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx9_vdata0_1>`, :ref:`vdata1<amdgpu_synid_gfx9_vdata1_1>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg_rtn_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg_rtn_b64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_b32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_b64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_rtn_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_rtn_b64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_src2_b32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_src2_b64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
EXP
-----------------------
@@ -199,8 +199,8 @@ EXP
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
- \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- exp :ref:`tgt<amdgpu_synid9_tgt>`, :ref:`vsrc0<amdgpu_synid9_src_exp>`, :ref:`vsrc1<amdgpu_synid9_src_exp>`, :ref:`vsrc2<amdgpu_synid9_src_exp>`, :ref:`vsrc3<amdgpu_synid9_src_exp>` :ref:`done<amdgpu_synid_done>` :ref:`compr<amdgpu_synid_compr>` :ref:`vm<amdgpu_synid_vm>`
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ exp :ref:`tgt<amdgpu_synid_gfx9_tgt>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc>`, :ref:`vsrc2<amdgpu_synid_gfx9_vsrc>`, :ref:`vsrc3<amdgpu_synid_gfx9_vsrc>` :ref:`done<amdgpu_synid_done>` :ref:`compr<amdgpu_synid_compr>` :ref:`vm<amdgpu_synid_vm>`
FLAT
-----------------------
@@ -208,321 +208,321 @@ FLAT
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
- \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- flat_atomic_add :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_add_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_and :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_and_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_cmpswap :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`b32x2<amdgpu_synid9_type_dev>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_cmpswap_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata128_0>`::ref:`b64x2<amdgpu_synid9_type_dev>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_dec :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`u32<amdgpu_synid9_type_dev>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_dec_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`u64<amdgpu_synid9_type_dev>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_inc :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`u32<amdgpu_synid9_type_dev>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_inc_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`u64<amdgpu_synid9_type_dev>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_or :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_or_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_smax :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`s32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`s32<amdgpu_synid9_type_dev>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_smax_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`s64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`s64<amdgpu_synid9_type_dev>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_smin :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`s32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`s32<amdgpu_synid9_type_dev>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_smin_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`s64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`s64<amdgpu_synid9_type_dev>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_sub :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_sub_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_swap :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_swap_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_umax :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`u32<amdgpu_synid9_type_dev>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_umax_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`u64<amdgpu_synid9_type_dev>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_umin :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`u32<amdgpu_synid9_type_dev>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_umin_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`u64<amdgpu_synid9_type_dev>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_xor :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_xor_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_dword :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_flat>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_dwordx2 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_flat>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_dwordx3 :ref:`vdst<amdgpu_synid9_vdst96_0>`, :ref:`vaddr<amdgpu_synid9_addr_flat>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_dwordx4 :ref:`vdst<amdgpu_synid9_vdst128_0>`, :ref:`vaddr<amdgpu_synid9_addr_flat>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_sbyte :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_flat>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_sbyte_d16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_flat>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_flat>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_short_d16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_flat>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_short_d16_hi :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_flat>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_sshort :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_flat>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_ubyte :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_flat>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_ubyte_d16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_flat>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_flat>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_ushort :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_flat>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_store_byte :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_store_byte_d16_hi :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_store_dword :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_store_dwordx2 :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_store_dwordx3 :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata96_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_store_dwordx4 :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata128_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_store_short :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_store_short_d16_hi :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_add :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_add_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_and :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_and_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_cmpswap :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`b32x2<amdgpu_synid9_type_dev>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_cmpswap_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata128_0>`::ref:`b64x2<amdgpu_synid9_type_dev>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_dec :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_dec_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_inc :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_inc_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_or :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_or_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_smax :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`s32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`s32<amdgpu_synid9_type_dev>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_smax_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`s64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`s64<amdgpu_synid9_type_dev>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_smin :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`s32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`s32<amdgpu_synid9_type_dev>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_smin_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`s64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`s64<amdgpu_synid9_type_dev>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_sub :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_sub_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_swap :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_swap_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_umax :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_umax_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_umin :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_umin_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_xor :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_xor_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_load_dword :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_load_dwordx2 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_load_dwordx3 :ref:`vdst<amdgpu_synid9_vdst96_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_load_dwordx4 :ref:`vdst<amdgpu_synid9_vdst128_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_load_sbyte :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_load_sbyte_d16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_load_short_d16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_load_short_d16_hi :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_load_sshort :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_load_ubyte :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_load_ubyte_d16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_load_ushort :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_store_byte :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_store_byte_d16_hi :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_store_dword :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_store_dwordx2 :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_store_dwordx3 :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata96_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_store_dwordx4 :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata128_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_store_short :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_store_short_d16_hi :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_load_dword :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_load_dwordx2 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_load_dwordx3 :ref:`vdst<amdgpu_synid9_vdst96_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_load_dwordx4 :ref:`vdst<amdgpu_synid9_vdst128_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_load_sbyte :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_load_sbyte_d16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_load_short_d16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_load_short_d16_hi :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_load_sshort :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_load_ubyte :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_load_ubyte_d16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_load_ushort :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_store_byte :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_store_byte_d16_hi :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_store_dword :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_store_dwordx2 :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_store_dwordx3 :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`vdata<amdgpu_synid9_vdata96_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_store_dwordx4 :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`vdata<amdgpu_synid9_vdata128_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_store_short :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- scratch_store_short_d16_hi :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ flat_atomic_add :ref:`vdst<amdgpu_synid_gfx9_vdst_4>`::ref:`opt<amdgpu_synid_gfx9_opt>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_add_x2 :ref:`vdst<amdgpu_synid_gfx9_vdst_5>`::ref:`opt<amdgpu_synid_gfx9_opt>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_and :ref:`vdst<amdgpu_synid_gfx9_vdst_4>`::ref:`opt<amdgpu_synid_gfx9_opt>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_and_x2 :ref:`vdst<amdgpu_synid_gfx9_vdst_5>`::ref:`opt<amdgpu_synid_gfx9_opt>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_cmpswap :ref:`vdst<amdgpu_synid_gfx9_vdst_4>`::ref:`opt<amdgpu_synid_gfx9_opt>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>`::ref:`b32x2<amdgpu_synid_gfx9_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_cmpswap_x2 :ref:`vdst<amdgpu_synid_gfx9_vdst_5>`::ref:`opt<amdgpu_synid_gfx9_opt>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_2>`::ref:`b64x2<amdgpu_synid_gfx9_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_dec :ref:`vdst<amdgpu_synid_gfx9_vdst_4>`::ref:`opt<amdgpu_synid_gfx9_opt>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_dec_x2 :ref:`vdst<amdgpu_synid_gfx9_vdst_5>`::ref:`opt<amdgpu_synid_gfx9_opt>`::ref:`u64<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>`::ref:`u64<amdgpu_synid_gfx9_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_inc :ref:`vdst<amdgpu_synid_gfx9_vdst_4>`::ref:`opt<amdgpu_synid_gfx9_opt>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_inc_x2 :ref:`vdst<amdgpu_synid_gfx9_vdst_5>`::ref:`opt<amdgpu_synid_gfx9_opt>`::ref:`u64<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>`::ref:`u64<amdgpu_synid_gfx9_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_or :ref:`vdst<amdgpu_synid_gfx9_vdst_4>`::ref:`opt<amdgpu_synid_gfx9_opt>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_or_x2 :ref:`vdst<amdgpu_synid_gfx9_vdst_5>`::ref:`opt<amdgpu_synid_gfx9_opt>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_smax :ref:`vdst<amdgpu_synid_gfx9_vdst_4>`::ref:`opt<amdgpu_synid_gfx9_opt>`::ref:`i32<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>`::ref:`i32<amdgpu_synid_gfx9_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_smax_x2 :ref:`vdst<amdgpu_synid_gfx9_vdst_5>`::ref:`opt<amdgpu_synid_gfx9_opt>`::ref:`i64<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>`::ref:`i64<amdgpu_synid_gfx9_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_smin :ref:`vdst<amdgpu_synid_gfx9_vdst_4>`::ref:`opt<amdgpu_synid_gfx9_opt>`::ref:`i32<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>`::ref:`i32<amdgpu_synid_gfx9_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_smin_x2 :ref:`vdst<amdgpu_synid_gfx9_vdst_5>`::ref:`opt<amdgpu_synid_gfx9_opt>`::ref:`i64<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>`::ref:`i64<amdgpu_synid_gfx9_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_sub :ref:`vdst<amdgpu_synid_gfx9_vdst_4>`::ref:`opt<amdgpu_synid_gfx9_opt>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_sub_x2 :ref:`vdst<amdgpu_synid_gfx9_vdst_5>`::ref:`opt<amdgpu_synid_gfx9_opt>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_swap :ref:`vdst<amdgpu_synid_gfx9_vdst_4>`::ref:`opt<amdgpu_synid_gfx9_opt>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_swap_x2 :ref:`vdst<amdgpu_synid_gfx9_vdst_5>`::ref:`opt<amdgpu_synid_gfx9_opt>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_umax :ref:`vdst<amdgpu_synid_gfx9_vdst_4>`::ref:`opt<amdgpu_synid_gfx9_opt>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_umax_x2 :ref:`vdst<amdgpu_synid_gfx9_vdst_5>`::ref:`opt<amdgpu_synid_gfx9_opt>`::ref:`u64<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>`::ref:`u64<amdgpu_synid_gfx9_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_umin :ref:`vdst<amdgpu_synid_gfx9_vdst_4>`::ref:`opt<amdgpu_synid_gfx9_opt>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_umin_x2 :ref:`vdst<amdgpu_synid_gfx9_vdst_5>`::ref:`opt<amdgpu_synid_gfx9_opt>`::ref:`u64<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>`::ref:`u64<amdgpu_synid_gfx9_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_xor :ref:`vdst<amdgpu_synid_gfx9_vdst_4>`::ref:`opt<amdgpu_synid_gfx9_opt>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_xor_x2 :ref:`vdst<amdgpu_synid_gfx9_vdst_5>`::ref:`opt<amdgpu_synid_gfx9_opt>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_dword :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx9_vdst_3>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_dwordx4 :ref:`vdst<amdgpu_synid_gfx9_vdst_2>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_sbyte :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_sbyte_d16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_short_d16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_short_d16_hi :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_sshort :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_ubyte :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_ubyte_d16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_ushort :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_store_byte :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_store_byte_d16_hi :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_store_dword :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_store_dwordx2 :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_store_dwordx3 :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_3>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_store_dwordx4 :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_2>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_store_short :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_store_short_d16_hi :ref:`vaddr<amdgpu_synid_gfx9_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_add :ref:`vdst<amdgpu_synid_gfx9_vdst_4>`::ref:`opt<amdgpu_synid_gfx9_opt>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_add_x2 :ref:`vdst<amdgpu_synid_gfx9_vdst_5>`::ref:`opt<amdgpu_synid_gfx9_opt>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_and :ref:`vdst<amdgpu_synid_gfx9_vdst_4>`::ref:`opt<amdgpu_synid_gfx9_opt>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_and_x2 :ref:`vdst<amdgpu_synid_gfx9_vdst_5>`::ref:`opt<amdgpu_synid_gfx9_opt>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_cmpswap :ref:`vdst<amdgpu_synid_gfx9_vdst_4>`::ref:`opt<amdgpu_synid_gfx9_opt>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>`::ref:`b32x2<amdgpu_synid_gfx9_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_cmpswap_x2 :ref:`vdst<amdgpu_synid_gfx9_vdst_5>`::ref:`opt<amdgpu_synid_gfx9_opt>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_2>`::ref:`b64x2<amdgpu_synid_gfx9_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_dec :ref:`vdst<amdgpu_synid_gfx9_vdst_4>`::ref:`opt<amdgpu_synid_gfx9_opt>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_dec_x2 :ref:`vdst<amdgpu_synid_gfx9_vdst_5>`::ref:`opt<amdgpu_synid_gfx9_opt>`::ref:`u64<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>`::ref:`u64<amdgpu_synid_gfx9_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_inc :ref:`vdst<amdgpu_synid_gfx9_vdst_4>`::ref:`opt<amdgpu_synid_gfx9_opt>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_inc_x2 :ref:`vdst<amdgpu_synid_gfx9_vdst_5>`::ref:`opt<amdgpu_synid_gfx9_opt>`::ref:`u64<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>`::ref:`u64<amdgpu_synid_gfx9_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_or :ref:`vdst<amdgpu_synid_gfx9_vdst_4>`::ref:`opt<amdgpu_synid_gfx9_opt>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_or_x2 :ref:`vdst<amdgpu_synid_gfx9_vdst_5>`::ref:`opt<amdgpu_synid_gfx9_opt>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_smax :ref:`vdst<amdgpu_synid_gfx9_vdst_4>`::ref:`opt<amdgpu_synid_gfx9_opt>`::ref:`i32<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>`::ref:`i32<amdgpu_synid_gfx9_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_smax_x2 :ref:`vdst<amdgpu_synid_gfx9_vdst_5>`::ref:`opt<amdgpu_synid_gfx9_opt>`::ref:`i64<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>`::ref:`i64<amdgpu_synid_gfx9_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_smin :ref:`vdst<amdgpu_synid_gfx9_vdst_4>`::ref:`opt<amdgpu_synid_gfx9_opt>`::ref:`i32<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>`::ref:`i32<amdgpu_synid_gfx9_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_smin_x2 :ref:`vdst<amdgpu_synid_gfx9_vdst_5>`::ref:`opt<amdgpu_synid_gfx9_opt>`::ref:`i64<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>`::ref:`i64<amdgpu_synid_gfx9_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_sub :ref:`vdst<amdgpu_synid_gfx9_vdst_4>`::ref:`opt<amdgpu_synid_gfx9_opt>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_sub_x2 :ref:`vdst<amdgpu_synid_gfx9_vdst_5>`::ref:`opt<amdgpu_synid_gfx9_opt>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_swap :ref:`vdst<amdgpu_synid_gfx9_vdst_4>`::ref:`opt<amdgpu_synid_gfx9_opt>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_swap_x2 :ref:`vdst<amdgpu_synid_gfx9_vdst_5>`::ref:`opt<amdgpu_synid_gfx9_opt>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_umax :ref:`vdst<amdgpu_synid_gfx9_vdst_4>`::ref:`opt<amdgpu_synid_gfx9_opt>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_umax_x2 :ref:`vdst<amdgpu_synid_gfx9_vdst_5>`::ref:`opt<amdgpu_synid_gfx9_opt>`::ref:`u64<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>`::ref:`u64<amdgpu_synid_gfx9_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_umin :ref:`vdst<amdgpu_synid_gfx9_vdst_4>`::ref:`opt<amdgpu_synid_gfx9_opt>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_umin_x2 :ref:`vdst<amdgpu_synid_gfx9_vdst_5>`::ref:`opt<amdgpu_synid_gfx9_opt>`::ref:`u64<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>`::ref:`u64<amdgpu_synid_gfx9_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_xor :ref:`vdst<amdgpu_synid_gfx9_vdst_4>`::ref:`opt<amdgpu_synid_gfx9_opt>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_xor_x2 :ref:`vdst<amdgpu_synid_gfx9_vdst_5>`::ref:`opt<amdgpu_synid_gfx9_opt>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_load_dword :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx9_vdst_3>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_load_dwordx4 :ref:`vdst<amdgpu_synid_gfx9_vdst_2>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_load_sbyte :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_load_sbyte_d16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_load_short_d16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_load_short_d16_hi :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_load_sshort :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_load_ubyte :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_load_ubyte_d16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_load_ushort :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_store_byte :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_store_byte_d16_hi :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_store_dword :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_store_dwordx2 :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_store_dwordx3 :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_3>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_store_dwordx4 :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_2>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_store_short :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_store_short_d16_hi :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>`, :ref:`saddr<amdgpu_synid_gfx9_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_load_dword :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx9_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx9_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx9_vdst_3>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx9_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_load_dwordx4 :ref:`vdst<amdgpu_synid_gfx9_vdst_2>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx9_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_load_sbyte :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx9_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_load_sbyte_d16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx9_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx9_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_load_short_d16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx9_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_load_short_d16_hi :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx9_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_load_sshort :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx9_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_load_ubyte :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx9_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_load_ubyte_d16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx9_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx9_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_load_ushort :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx9_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_store_byte :ref:`vaddr<amdgpu_synid_gfx9_vaddr_3>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>`, :ref:`saddr<amdgpu_synid_gfx9_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_store_byte_d16_hi :ref:`vaddr<amdgpu_synid_gfx9_vaddr_3>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>`, :ref:`saddr<amdgpu_synid_gfx9_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_store_dword :ref:`vaddr<amdgpu_synid_gfx9_vaddr_3>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>`, :ref:`saddr<amdgpu_synid_gfx9_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_store_dwordx2 :ref:`vaddr<amdgpu_synid_gfx9_vaddr_3>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_1>`, :ref:`saddr<amdgpu_synid_gfx9_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_store_dwordx3 :ref:`vaddr<amdgpu_synid_gfx9_vaddr_3>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_3>`, :ref:`saddr<amdgpu_synid_gfx9_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_store_dwordx4 :ref:`vaddr<amdgpu_synid_gfx9_vaddr_3>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_2>`, :ref:`saddr<amdgpu_synid_gfx9_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_store_short :ref:`vaddr<amdgpu_synid_gfx9_vaddr_3>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>`, :ref:`saddr<amdgpu_synid_gfx9_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_store_short_d16_hi :ref:`vaddr<amdgpu_synid_gfx9_vaddr_3>`, :ref:`vdata<amdgpu_synid_gfx9_vdata>`, :ref:`saddr<amdgpu_synid_gfx9_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
MIMG
-----------------------
.. parsed-literal::
- **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
- \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- image_atomic_add :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_and :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_cmpswap :ref:`vdata<amdgpu_synid9_data_mimg_atomic_cmp>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_dec :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_inc :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_or :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_smax :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_smin :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_sub :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_swap :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_umax :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_umin :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_xor :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_gather4 :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_b :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_b_cl :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_b_cl_o :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_b_o :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_b :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_b_cl :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_b_cl_o :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_b_o :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_cl :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_cl_o :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_l :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_l_o :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_lz :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_lz_o :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_o :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_cl :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_cl_o :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_l :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_l_o :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_lz :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_lz_o :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_o :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_get_lod :ref:`vdst<amdgpu_synid9_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_get_resinfo :ref:`vdst<amdgpu_synid9_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_load :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_load_mip :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_load_mip_pck :ref:`vdst<amdgpu_synid9_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_load_mip_pck_sgn :ref:`vdst<amdgpu_synid9_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_load_pck :ref:`vdst<amdgpu_synid9_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_load_pck_sgn :ref:`vdst<amdgpu_synid9_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_b :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_b_cl :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_b_cl_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_b_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_b :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_b_cl :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_b_cl_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_b_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_cd :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_cd_cl :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_cd_cl_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_cd_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_cl :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_cl_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_d :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_d_cl :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_d_cl_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_d_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_l :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_l_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_lz :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_lz_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_cd :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_cd_cl :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_cd_cl_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_cd_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_cl :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_cl_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_d :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_d_cl :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_d_cl_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_d_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_l :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_l_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_lz :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_lz_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_store :ref:`vdata<amdgpu_synid9_data_mimg_store_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_store_mip :ref:`vdata<amdgpu_synid9_data_mimg_store_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
- image_store_mip_pck :ref:`vdata<amdgpu_synid9_data_mimg_store>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_store_pck :ref:`vdata<amdgpu_synid9_data_mimg_store>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ image_atomic_add :ref:`vdata<amdgpu_synid_gfx9_vdata_4>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_and :ref:`vdata<amdgpu_synid_gfx9_vdata_4>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_cmpswap :ref:`vdata<amdgpu_synid_gfx9_vdata_5>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_dec :ref:`vdata<amdgpu_synid_gfx9_vdata_4>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_inc :ref:`vdata<amdgpu_synid_gfx9_vdata_4>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_or :ref:`vdata<amdgpu_synid_gfx9_vdata_4>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_smax :ref:`vdata<amdgpu_synid_gfx9_vdata_4>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_smin :ref:`vdata<amdgpu_synid_gfx9_vdata_4>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_sub :ref:`vdata<amdgpu_synid_gfx9_vdata_4>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_swap :ref:`vdata<amdgpu_synid_gfx9_vdata_4>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_umax :ref:`vdata<amdgpu_synid_gfx9_vdata_4>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_umin :ref:`vdata<amdgpu_synid_gfx9_vdata_4>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_xor :ref:`vdata<amdgpu_synid_gfx9_vdata_4>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4 :ref:`vdst<amdgpu_synid_gfx9_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_b :ref:`vdst<amdgpu_synid_gfx9_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_b_cl :ref:`vdst<amdgpu_synid_gfx9_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_b_cl_o :ref:`vdst<amdgpu_synid_gfx9_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_b_o :ref:`vdst<amdgpu_synid_gfx9_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c :ref:`vdst<amdgpu_synid_gfx9_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_b :ref:`vdst<amdgpu_synid_gfx9_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_b_cl :ref:`vdst<amdgpu_synid_gfx9_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_b_cl_o :ref:`vdst<amdgpu_synid_gfx9_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_b_o :ref:`vdst<amdgpu_synid_gfx9_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_cl :ref:`vdst<amdgpu_synid_gfx9_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_cl_o :ref:`vdst<amdgpu_synid_gfx9_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_l :ref:`vdst<amdgpu_synid_gfx9_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_l_o :ref:`vdst<amdgpu_synid_gfx9_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_lz :ref:`vdst<amdgpu_synid_gfx9_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_lz_o :ref:`vdst<amdgpu_synid_gfx9_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_o :ref:`vdst<amdgpu_synid_gfx9_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_cl :ref:`vdst<amdgpu_synid_gfx9_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_cl_o :ref:`vdst<amdgpu_synid_gfx9_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_l :ref:`vdst<amdgpu_synid_gfx9_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_l_o :ref:`vdst<amdgpu_synid_gfx9_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_lz :ref:`vdst<amdgpu_synid_gfx9_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_lz_o :ref:`vdst<amdgpu_synid_gfx9_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_o :ref:`vdst<amdgpu_synid_gfx9_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_get_lod :ref:`vdst<amdgpu_synid_gfx9_vdst_7>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_get_resinfo :ref:`vdst<amdgpu_synid_gfx9_vdst_7>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_load :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_load_mip :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_load_mip_pck :ref:`vdst<amdgpu_synid_gfx9_vdst_7>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_load_mip_pck_sgn :ref:`vdst<amdgpu_synid_gfx9_vdst_7>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_load_pck :ref:`vdst<amdgpu_synid_gfx9_vdst_7>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_load_pck_sgn :ref:`vdst<amdgpu_synid_gfx9_vdst_7>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_b :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_b_cl :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_b_cl_o :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_b_o :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_b :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_b_cl :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_b_cl_o :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_b_o :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cd :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cd_cl :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cd_cl_o :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cd_o :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cl :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cl_o :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_d :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_d_cl :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_d_cl_o :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_d_o :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_l :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_l_o :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_lz :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_lz_o :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_o :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cd :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cd_cl :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cd_cl_o :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cd_o :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cl :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cl_o :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_d :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_d_cl :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_d_cl_o :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_d_o :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_l :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_l_o :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_lz :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_lz_o :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_o :ref:`vdst<amdgpu_synid_gfx9_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx9_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_store :ref:`vdata<amdgpu_synid_gfx9_vdata_6>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_store_mip :ref:`vdata<amdgpu_synid_gfx9_vdata_6>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_store_mip_pck :ref:`vdata<amdgpu_synid_gfx9_vdata_7>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_store_pck :ref:`vdata<amdgpu_synid_gfx9_vdata_7>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
MTBUF
-----------------------
.. parsed-literal::
- **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
- \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- tbuffer_load_format_d16_x :ref:`vdst<amdgpu_synid9_dst_buf_32>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- tbuffer_load_format_d16_xy :ref:`vdst<amdgpu_synid9_dst_buf_32>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- tbuffer_load_format_d16_xyz :ref:`vdst<amdgpu_synid9_dst_buf_64>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- tbuffer_load_format_d16_xyzw :ref:`vdst<amdgpu_synid9_dst_buf_64>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- tbuffer_load_format_x :ref:`vdst<amdgpu_synid9_dst_buf_32>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- tbuffer_load_format_xy :ref:`vdst<amdgpu_synid9_dst_buf_64>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- tbuffer_load_format_xyz :ref:`vdst<amdgpu_synid9_dst_buf_96>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- tbuffer_load_format_xyzw :ref:`vdst<amdgpu_synid9_dst_buf_128>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- tbuffer_store_format_d16_x :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- tbuffer_store_format_d16_xy :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- tbuffer_store_format_d16_xyz :ref:`vdata<amdgpu_synid9_vdata64_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- tbuffer_store_format_d16_xyzw :ref:`vdata<amdgpu_synid9_vdata64_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- tbuffer_store_format_x :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- tbuffer_store_format_xy :ref:`vdata<amdgpu_synid9_vdata64_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- tbuffer_store_format_xyz :ref:`vdata<amdgpu_synid9_vdata96_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- tbuffer_store_format_xyzw :ref:`vdata<amdgpu_synid9_vdata128_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ tbuffer_load_format_d16_x :ref:`vdst<amdgpu_synid_gfx9_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_load_format_d16_xy :ref:`vdst<amdgpu_synid_gfx9_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_load_format_d16_xyz :ref:`vdst<amdgpu_synid_gfx9_vdst_10>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_load_format_d16_xyzw :ref:`vdst<amdgpu_synid_gfx9_vdst_10>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_load_format_x :ref:`vdst<amdgpu_synid_gfx9_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_load_format_xy :ref:`vdst<amdgpu_synid_gfx9_vdst_10>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_load_format_xyz :ref:`vdst<amdgpu_synid_gfx9_vdst_11>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_load_format_xyzw :ref:`vdst<amdgpu_synid_gfx9_vdst_12>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_store_format_d16_x :ref:`vdata<amdgpu_synid_gfx9_vdata>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_store_format_d16_xy :ref:`vdata<amdgpu_synid_gfx9_vdata>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_store_format_d16_xyz :ref:`vdata<amdgpu_synid_gfx9_vdata_1>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_store_format_d16_xyzw :ref:`vdata<amdgpu_synid_gfx9_vdata_1>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_store_format_x :ref:`vdata<amdgpu_synid_gfx9_vdata>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_store_format_xy :ref:`vdata<amdgpu_synid_gfx9_vdata_1>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_store_format_xyz :ref:`vdata<amdgpu_synid_gfx9_vdata_3>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_store_format_xyzw :ref:`vdata<amdgpu_synid_gfx9_vdata_2>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
MUBUF
-----------------------
.. parsed-literal::
- **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
- \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- buffer_atomic_add :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_add_x2 :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_and :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_and_x2 :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_cmpswap :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`b32x2<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_cmpswap_x2 :ref:`vdata<amdgpu_synid9_data_buf_atomic128>`::ref:`dst<amdgpu_synid9_ret>`::ref:`b64x2<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_dec :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_dec_x2 :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_inc :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_inc_x2 :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_or :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_or_x2 :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_smax :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_smax_x2 :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_smin :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_smin_x2 :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_sub :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_sub_x2 :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_swap :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_swap_x2 :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_umax :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_umax_x2 :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_umin :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_umin_x2 :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_xor :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_xor_x2 :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_dword :ref:`vdst<amdgpu_synid9_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_load_dwordx2 :ref:`vdst<amdgpu_synid9_dst_buf_64>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_dwordx3 :ref:`vdst<amdgpu_synid9_dst_buf_96>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_dwordx4 :ref:`vdst<amdgpu_synid9_dst_buf_128>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_format_d16_hi_x :ref:`vdst<amdgpu_synid9_dst_buf_32>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_format_d16_x :ref:`vdst<amdgpu_synid9_dst_buf_32>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_format_d16_xy :ref:`vdst<amdgpu_synid9_dst_buf_32>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_format_d16_xyz :ref:`vdst<amdgpu_synid9_dst_buf_64>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_format_d16_xyzw :ref:`vdst<amdgpu_synid9_dst_buf_64>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_format_x :ref:`vdst<amdgpu_synid9_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_load_format_xy :ref:`vdst<amdgpu_synid9_dst_buf_64>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_format_xyz :ref:`vdst<amdgpu_synid9_dst_buf_96>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_format_xyzw :ref:`vdst<amdgpu_synid9_dst_buf_128>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_sbyte :ref:`vdst<amdgpu_synid9_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_load_sbyte_d16 :ref:`vdst<amdgpu_synid9_dst_buf_32>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid9_dst_buf_32>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_short_d16 :ref:`vdst<amdgpu_synid9_dst_buf_32>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_short_d16_hi :ref:`vdst<amdgpu_synid9_dst_buf_32>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_sshort :ref:`vdst<amdgpu_synid9_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_load_ubyte :ref:`vdst<amdgpu_synid9_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_load_ubyte_d16 :ref:`vdst<amdgpu_synid9_dst_buf_32>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid9_dst_buf_32>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_ushort :ref:`vdst<amdgpu_synid9_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_store_byte :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_byte_d16_hi :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_dword :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_dwordx2 :ref:`vdata<amdgpu_synid9_vdata64_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_dwordx3 :ref:`vdata<amdgpu_synid9_vdata96_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_dwordx4 :ref:`vdata<amdgpu_synid9_vdata128_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_d16_hi_x :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_d16_x :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_d16_xy :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_d16_xyz :ref:`vdata<amdgpu_synid9_vdata64_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_d16_xyzw :ref:`vdata<amdgpu_synid9_vdata64_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_x :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_xy :ref:`vdata<amdgpu_synid9_vdata64_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_xyz :ref:`vdata<amdgpu_synid9_vdata96_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_xyzw :ref:`vdata<amdgpu_synid9_vdata128_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_lds_dword :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`lds<amdgpu_synid_lds>`
- buffer_store_short :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_short_d16_hi :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ buffer_atomic_add :ref:`vdata<amdgpu_synid_gfx9_vdata_8>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_add_x2 :ref:`vdata<amdgpu_synid_gfx9_vdata_9>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_and :ref:`vdata<amdgpu_synid_gfx9_vdata_8>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_and_x2 :ref:`vdata<amdgpu_synid_gfx9_vdata_9>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_cmpswap :ref:`vdata<amdgpu_synid_gfx9_vdata_9>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`b32x2<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_cmpswap_x2 :ref:`vdata<amdgpu_synid_gfx9_vdata_10>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`b64x2<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_dec :ref:`vdata<amdgpu_synid_gfx9_vdata_8>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_dec_x2 :ref:`vdata<amdgpu_synid_gfx9_vdata_9>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`u64<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_inc :ref:`vdata<amdgpu_synid_gfx9_vdata_8>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_inc_x2 :ref:`vdata<amdgpu_synid_gfx9_vdata_9>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`u64<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_or :ref:`vdata<amdgpu_synid_gfx9_vdata_8>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_or_x2 :ref:`vdata<amdgpu_synid_gfx9_vdata_9>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smax :ref:`vdata<amdgpu_synid_gfx9_vdata_8>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`i32<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smax_x2 :ref:`vdata<amdgpu_synid_gfx9_vdata_9>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`i64<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smin :ref:`vdata<amdgpu_synid_gfx9_vdata_8>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`i32<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smin_x2 :ref:`vdata<amdgpu_synid_gfx9_vdata_9>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`i64<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_sub :ref:`vdata<amdgpu_synid_gfx9_vdata_8>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_sub_x2 :ref:`vdata<amdgpu_synid_gfx9_vdata_9>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_swap :ref:`vdata<amdgpu_synid_gfx9_vdata_8>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_swap_x2 :ref:`vdata<amdgpu_synid_gfx9_vdata_9>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umax :ref:`vdata<amdgpu_synid_gfx9_vdata_8>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umax_x2 :ref:`vdata<amdgpu_synid_gfx9_vdata_9>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`u64<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umin :ref:`vdata<amdgpu_synid_gfx9_vdata_8>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umin_x2 :ref:`vdata<amdgpu_synid_gfx9_vdata_9>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`u64<amdgpu_synid_gfx9_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_xor :ref:`vdata<amdgpu_synid_gfx9_vdata_8>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_xor_x2 :ref:`vdata<amdgpu_synid_gfx9_vdata_9>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_dword :ref:`vdst<amdgpu_synid_gfx9_vdst_13>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx9_vdst_10>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx9_vdst_11>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_dwordx4 :ref:`vdst<amdgpu_synid_gfx9_vdst_12>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_format_d16_hi_x :ref:`vdst<amdgpu_synid_gfx9_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_format_d16_x :ref:`vdst<amdgpu_synid_gfx9_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_format_d16_xy :ref:`vdst<amdgpu_synid_gfx9_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_format_d16_xyz :ref:`vdst<amdgpu_synid_gfx9_vdst_10>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_format_d16_xyzw :ref:`vdst<amdgpu_synid_gfx9_vdst_10>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_format_x :ref:`vdst<amdgpu_synid_gfx9_vdst_13>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_format_xy :ref:`vdst<amdgpu_synid_gfx9_vdst_10>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_format_xyz :ref:`vdst<amdgpu_synid_gfx9_vdst_11>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_format_xyzw :ref:`vdst<amdgpu_synid_gfx9_vdst_12>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_sbyte :ref:`vdst<amdgpu_synid_gfx9_vdst_13>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_sbyte_d16 :ref:`vdst<amdgpu_synid_gfx9_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid_gfx9_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_short_d16 :ref:`vdst<amdgpu_synid_gfx9_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_short_d16_hi :ref:`vdst<amdgpu_synid_gfx9_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_sshort :ref:`vdst<amdgpu_synid_gfx9_vdst_13>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_ubyte :ref:`vdst<amdgpu_synid_gfx9_vdst_13>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_ubyte_d16 :ref:`vdst<amdgpu_synid_gfx9_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid_gfx9_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_ushort :ref:`vdst<amdgpu_synid_gfx9_vdst_13>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_store_byte :ref:`vdata<amdgpu_synid_gfx9_vdata>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_byte_d16_hi :ref:`vdata<amdgpu_synid_gfx9_vdata>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dword :ref:`vdata<amdgpu_synid_gfx9_vdata>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dwordx2 :ref:`vdata<amdgpu_synid_gfx9_vdata_1>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dwordx3 :ref:`vdata<amdgpu_synid_gfx9_vdata_3>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dwordx4 :ref:`vdata<amdgpu_synid_gfx9_vdata_2>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_d16_hi_x :ref:`vdata<amdgpu_synid_gfx9_vdata>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_d16_x :ref:`vdata<amdgpu_synid_gfx9_vdata>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_d16_xy :ref:`vdata<amdgpu_synid_gfx9_vdata>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_d16_xyz :ref:`vdata<amdgpu_synid_gfx9_vdata_1>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_d16_xyzw :ref:`vdata<amdgpu_synid_gfx9_vdata_1>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_x :ref:`vdata<amdgpu_synid_gfx9_vdata>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_xy :ref:`vdata<amdgpu_synid_gfx9_vdata_1>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_xyz :ref:`vdata<amdgpu_synid_gfx9_vdata_3>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_xyzw :ref:`vdata<amdgpu_synid_gfx9_vdata_2>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_lds_dword :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_store_short :ref:`vdata<amdgpu_synid_gfx9_vdata>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_short_d16_hi :ref:`vdata<amdgpu_synid_gfx9_vdata>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx9_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_wbinvl1
buffer_wbinvl1_vol
@@ -532,91 +532,91 @@ SMEM
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
- \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- s_atc_probe :ref:`imm3<amdgpu_synid9_perm_smem>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>`
- s_atc_probe_buffer :ref:`imm3<amdgpu_synid9_perm_smem>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>`
- s_atomic_add :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_add_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_and :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_and_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_cmpswap :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`b32x2<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_cmpswap_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic128>`::ref:`dst<amdgpu_synid9_ret>`::ref:`b64x2<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_dec :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_dec_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_inc :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_inc_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_or :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_or_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_smax :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s32<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_smax_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s64<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_smin :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s32<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_smin_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s64<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_sub :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_sub_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_swap :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_swap_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_umax :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_umax_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_umin :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_umin_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_xor :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_xor_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_add :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_add_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_and :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_and_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_cmpswap :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`b32x2<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_cmpswap_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic128>`::ref:`dst<amdgpu_synid9_ret>`::ref:`b64x2<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_dec :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_dec_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_inc :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_inc_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_or :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_or_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_smax :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s32<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_smax_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s64<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_smin :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s32<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_smin_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s64<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_sub :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_sub_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_swap :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_swap_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_umax :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_umax_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_umin :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_umin_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_xor :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_xor_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_load_dword :ref:`sdst<amdgpu_synid9_sdst32_0>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_load_dwordx16 :ref:`sdst<amdgpu_synid9_sdst512_0>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_load_dwordx2 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_load_dwordx4 :ref:`sdst<amdgpu_synid9_sdst128_0>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_load_dwordx8 :ref:`sdst<amdgpu_synid9_sdst256_0>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_store_dword :ref:`sdata<amdgpu_synid9_sdata32_0>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_store_dwordx2 :ref:`sdata<amdgpu_synid9_sdata64_0>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_store_dwordx4 :ref:`sdata<amdgpu_synid9_sdata128_0>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
- s_dcache_discard :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>`
- s_dcache_discard_x2 :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>`
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_atc_probe :ref:`probe<amdgpu_synid_gfx9_probe>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>`
+ s_atc_probe_buffer :ref:`probe<amdgpu_synid_gfx9_probe>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>`
+ s_atomic_add :ref:`sdata<amdgpu_synid_gfx9_sdata>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_add_x2 :ref:`sdata<amdgpu_synid_gfx9_sdata_1>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_and :ref:`sdata<amdgpu_synid_gfx9_sdata>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_and_x2 :ref:`sdata<amdgpu_synid_gfx9_sdata_1>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_cmpswap :ref:`sdata<amdgpu_synid_gfx9_sdata_1>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`b32x2<amdgpu_synid_gfx9_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_cmpswap_x2 :ref:`sdata<amdgpu_synid_gfx9_sdata_2>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`b64x2<amdgpu_synid_gfx9_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_dec :ref:`sdata<amdgpu_synid_gfx9_sdata>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_dec_x2 :ref:`sdata<amdgpu_synid_gfx9_sdata_1>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`u64<amdgpu_synid_gfx9_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_inc :ref:`sdata<amdgpu_synid_gfx9_sdata>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_inc_x2 :ref:`sdata<amdgpu_synid_gfx9_sdata_1>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`u64<amdgpu_synid_gfx9_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_or :ref:`sdata<amdgpu_synid_gfx9_sdata>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_or_x2 :ref:`sdata<amdgpu_synid_gfx9_sdata_1>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_smax :ref:`sdata<amdgpu_synid_gfx9_sdata>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`i32<amdgpu_synid_gfx9_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_smax_x2 :ref:`sdata<amdgpu_synid_gfx9_sdata_1>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`i64<amdgpu_synid_gfx9_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_smin :ref:`sdata<amdgpu_synid_gfx9_sdata>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`i32<amdgpu_synid_gfx9_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_smin_x2 :ref:`sdata<amdgpu_synid_gfx9_sdata_1>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`i64<amdgpu_synid_gfx9_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_sub :ref:`sdata<amdgpu_synid_gfx9_sdata>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_sub_x2 :ref:`sdata<amdgpu_synid_gfx9_sdata_1>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_swap :ref:`sdata<amdgpu_synid_gfx9_sdata>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_swap_x2 :ref:`sdata<amdgpu_synid_gfx9_sdata_1>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_umax :ref:`sdata<amdgpu_synid_gfx9_sdata>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_umax_x2 :ref:`sdata<amdgpu_synid_gfx9_sdata_1>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`u64<amdgpu_synid_gfx9_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_umin :ref:`sdata<amdgpu_synid_gfx9_sdata>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_umin_x2 :ref:`sdata<amdgpu_synid_gfx9_sdata_1>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`u64<amdgpu_synid_gfx9_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_xor :ref:`sdata<amdgpu_synid_gfx9_sdata>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_xor_x2 :ref:`sdata<amdgpu_synid_gfx9_sdata_1>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_add :ref:`sdata<amdgpu_synid_gfx9_sdata>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_add_x2 :ref:`sdata<amdgpu_synid_gfx9_sdata_1>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_and :ref:`sdata<amdgpu_synid_gfx9_sdata>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_and_x2 :ref:`sdata<amdgpu_synid_gfx9_sdata_1>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_cmpswap :ref:`sdata<amdgpu_synid_gfx9_sdata_1>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`b32x2<amdgpu_synid_gfx9_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_cmpswap_x2 :ref:`sdata<amdgpu_synid_gfx9_sdata_2>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`b64x2<amdgpu_synid_gfx9_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_dec :ref:`sdata<amdgpu_synid_gfx9_sdata>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_dec_x2 :ref:`sdata<amdgpu_synid_gfx9_sdata_1>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`u64<amdgpu_synid_gfx9_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_inc :ref:`sdata<amdgpu_synid_gfx9_sdata>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_inc_x2 :ref:`sdata<amdgpu_synid_gfx9_sdata_1>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`u64<amdgpu_synid_gfx9_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_or :ref:`sdata<amdgpu_synid_gfx9_sdata>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_or_x2 :ref:`sdata<amdgpu_synid_gfx9_sdata_1>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_smax :ref:`sdata<amdgpu_synid_gfx9_sdata>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`i32<amdgpu_synid_gfx9_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_smax_x2 :ref:`sdata<amdgpu_synid_gfx9_sdata_1>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`i64<amdgpu_synid_gfx9_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_smin :ref:`sdata<amdgpu_synid_gfx9_sdata>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`i32<amdgpu_synid_gfx9_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_smin_x2 :ref:`sdata<amdgpu_synid_gfx9_sdata_1>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`i64<amdgpu_synid_gfx9_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_sub :ref:`sdata<amdgpu_synid_gfx9_sdata>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_sub_x2 :ref:`sdata<amdgpu_synid_gfx9_sdata_1>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_swap :ref:`sdata<amdgpu_synid_gfx9_sdata>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_swap_x2 :ref:`sdata<amdgpu_synid_gfx9_sdata_1>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_umax :ref:`sdata<amdgpu_synid_gfx9_sdata>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_umax_x2 :ref:`sdata<amdgpu_synid_gfx9_sdata_1>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`u64<amdgpu_synid_gfx9_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_umin :ref:`sdata<amdgpu_synid_gfx9_sdata>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_umin_x2 :ref:`sdata<amdgpu_synid_gfx9_sdata_1>`::ref:`dst<amdgpu_synid_gfx9_dst>`::ref:`u64<amdgpu_synid_gfx9_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_xor :ref:`sdata<amdgpu_synid_gfx9_sdata>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_xor_x2 :ref:`sdata<amdgpu_synid_gfx9_sdata_1>`::ref:`dst<amdgpu_synid_gfx9_dst>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_load_dword :ref:`sdst<amdgpu_synid_gfx9_sdst>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_load_dwordx16 :ref:`sdst<amdgpu_synid_gfx9_sdst_1>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx9_sdst_3>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_load_dwordx8 :ref:`sdst<amdgpu_synid_gfx9_sdst_4>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_store_dword :ref:`sdata<amdgpu_synid_gfx9_sdata_3>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_store_dwordx2 :ref:`sdata<amdgpu_synid_gfx9_sdata_4>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_store_dwordx4 :ref:`sdata<amdgpu_synid_gfx9_sdata_5>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_dcache_discard :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>`
+ s_dcache_discard_x2 :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>`
s_dcache_inv
s_dcache_inv_vol
s_dcache_wb
s_dcache_wb_vol
- s_load_dword :ref:`sdst<amdgpu_synid9_sdst32_0>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_load_dwordx16 :ref:`sdst<amdgpu_synid9_sdst512_0>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_load_dwordx2 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_load_dwordx4 :ref:`sdst<amdgpu_synid9_sdst128_0>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_load_dwordx8 :ref:`sdst<amdgpu_synid9_sdst256_0>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_memrealtime :ref:`sdst<amdgpu_synid9_sdst64_0>`
- s_memtime :ref:`sdst<amdgpu_synid9_sdst64_0>`
- s_scratch_load_dword :ref:`sdst<amdgpu_synid9_sdst32_0>`, :ref:`sbase<amdgpu_synid9_base_smem_scratch>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_scratch_load_dwordx2 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`sbase<amdgpu_synid9_base_smem_scratch>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_scratch_load_dwordx4 :ref:`sdst<amdgpu_synid9_sdst128_0>`, :ref:`sbase<amdgpu_synid9_base_smem_scratch>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_scratch_store_dword :ref:`sdata<amdgpu_synid9_sdata32_0>`, :ref:`sbase<amdgpu_synid9_base_smem_scratch>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_scratch_store_dwordx2 :ref:`sdata<amdgpu_synid9_sdata64_0>`, :ref:`sbase<amdgpu_synid9_base_smem_scratch>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_scratch_store_dwordx4 :ref:`sdata<amdgpu_synid9_sdata128_0>`, :ref:`sbase<amdgpu_synid9_base_smem_scratch>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_store_dword :ref:`sdata<amdgpu_synid9_sdata32_0>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_store_dwordx2 :ref:`sdata<amdgpu_synid9_sdata64_0>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
- s_store_dwordx4 :ref:`sdata<amdgpu_synid9_sdata128_0>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_load_dword :ref:`sdst<amdgpu_synid_gfx9_sdst>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_load_dwordx16 :ref:`sdst<amdgpu_synid_gfx9_sdst_1>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx9_sdst_3>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_load_dwordx8 :ref:`sdst<amdgpu_synid_gfx9_sdst_4>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_memrealtime :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`::ref:`b64<amdgpu_synid_gfx9_type_deviation>`
+ s_memtime :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`::ref:`b64<amdgpu_synid_gfx9_type_deviation>`
+ s_scratch_load_dword :ref:`sdst<amdgpu_synid_gfx9_sdst>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_2>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_scratch_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_2>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_scratch_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx9_sdst_3>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_2>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_scratch_store_dword :ref:`sdata<amdgpu_synid_gfx9_sdata_3>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_2>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_scratch_store_dwordx2 :ref:`sdata<amdgpu_synid_gfx9_sdata_4>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_2>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_scratch_store_dwordx4 :ref:`sdata<amdgpu_synid_gfx9_sdata_5>`, :ref:`sbase<amdgpu_synid_gfx9_sbase_2>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_store_dword :ref:`sdata<amdgpu_synid_gfx9_sdata_3>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_store_dwordx2 :ref:`sdata<amdgpu_synid_gfx9_sdata_4>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_store_dwordx4 :ref:`sdata<amdgpu_synid_gfx9_sdata_5>`, :ref:`sbase<amdgpu_synid_gfx9_sbase>`, :ref:`soffset<amdgpu_synid_gfx9_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
SOP1
-----------------------
@@ -624,122 +624,122 @@ SOP1
.. parsed-literal::
**INSTRUCTION** **DST** **SRC**
- \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- s_abs_i32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
- s_and_saveexec_b64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
- s_andn1_saveexec_b64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
- s_andn1_wrexec_b64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
- s_andn2_saveexec_b64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
- s_andn2_wrexec_b64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
- s_bcnt0_i32_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
- s_bcnt0_i32_b64 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
- s_bcnt1_i32_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
- s_bcnt1_i32_b64 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
- s_bitreplicate_b64_b32 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
- s_bitset0_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
- s_bitset0_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`::ref:`b32<amdgpu_synid9_type_dev>`
- s_bitset1_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
- s_bitset1_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`::ref:`b32<amdgpu_synid9_type_dev>`
- s_brev_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
- s_brev_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
- s_cbranch_join :ref:`ssrc<amdgpu_synid9_ssrc32_1>`
- s_cmov_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
- s_cmov_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
- s_ff0_i32_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
- s_ff0_i32_b64 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
- s_ff1_i32_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
- s_ff1_i32_b64 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
- s_flbit_i32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
- s_flbit_i32_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
- s_flbit_i32_b64 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
- s_flbit_i32_i64 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
- s_getpc_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`
- s_mov_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
- s_mov_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
- s_movreld_b32 :ref:`sdst<amdgpu_synid9_sdst32_0>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
- s_movreld_b64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
- s_movrels_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_1>`
- s_movrels_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc<amdgpu_synid9_ssrc64_1>`
- s_nand_saveexec_b64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
- s_nor_saveexec_b64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
- s_not_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
- s_not_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
- s_or_saveexec_b64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
- s_orn1_saveexec_b64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
- s_orn2_saveexec_b64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
- s_quadmask_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
- s_quadmask_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
- s_rfe_b64 :ref:`ssrc<amdgpu_synid9_ssrc64_1>`
- s_set_gpr_idx_idx :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
- s_setpc_b64 :ref:`ssrc<amdgpu_synid9_ssrc64_1>`
- s_sext_i32_i16 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
- s_sext_i32_i8 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
- s_swappc_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc<amdgpu_synid9_ssrc64_1>`
- s_wqm_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
- s_wqm_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
- s_xnor_saveexec_b64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
- s_xor_saveexec_b64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_abs_i32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc>`
+ s_and_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc_1>`
+ s_andn1_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc_1>`
+ s_andn1_wrexec_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc_1>`
+ s_andn2_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc_1>`
+ s_andn2_wrexec_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc_1>`
+ s_bcnt0_i32_b32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc>`
+ s_bcnt0_i32_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc_1>`
+ s_bcnt1_i32_b32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc>`
+ s_bcnt1_i32_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc_1>`
+ s_bitreplicate_b64_b32 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc>`
+ s_bitset0_b32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc>`
+ s_bitset0_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`
+ s_bitset1_b32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc>`
+ s_bitset1_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`
+ s_brev_b32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc>`
+ s_brev_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc_1>`
+ s_cbranch_join :ref:`ssrc<amdgpu_synid_gfx9_ssrc_2>`
+ s_cmov_b32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc>`
+ s_cmov_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc_1>`
+ s_ff0_i32_b32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc>`
+ s_ff0_i32_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc_1>`
+ s_ff1_i32_b32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc>`
+ s_ff1_i32_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc_1>`
+ s_flbit_i32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc>`
+ s_flbit_i32_b32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc>`
+ s_flbit_i32_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc_1>`
+ s_flbit_i32_i64 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc_1>`
+ s_getpc_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`
+ s_mov_b32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc>`
+ s_mov_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc_1>`
+ s_movreld_b32 :ref:`sdst<amdgpu_synid_gfx9_sdst>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc>`
+ s_movreld_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc_1>`
+ s_movrels_b32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc_2>`
+ s_movrels_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc_3>`
+ s_nand_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc_1>`
+ s_nor_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc_1>`
+ s_not_b32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc>`
+ s_not_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc_1>`
+ s_or_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc_1>`
+ s_orn1_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc_1>`
+ s_orn2_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc_1>`
+ s_quadmask_b32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc>`
+ s_quadmask_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc_1>`
+ s_rfe_b64 :ref:`ssrc<amdgpu_synid_gfx9_ssrc_3>`
+ s_set_gpr_idx_idx :ref:`ssrc<amdgpu_synid_gfx9_ssrc>`
+ s_setpc_b64 :ref:`ssrc<amdgpu_synid_gfx9_ssrc_3>`
+ s_sext_i32_i16 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc>`
+ s_sext_i32_i8 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc>`
+ s_swappc_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc_3>`
+ s_wqm_b32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc>`
+ s_wqm_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc_1>`
+ s_xnor_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc_1>`
+ s_xor_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc_1>`
SOP2
-----------------------
.. parsed-literal::
- **INSTRUCTION** **DST** **SRC0** **SRC1**
- \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- s_abs
diff _i32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_add_i32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_add_u32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_addc_u32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_and_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_and_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc64_0>`
- s_andn2_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_andn2_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc64_0>`
- s_ashr_i32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`
- s_ashr_i64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`
- s_bfe_i32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`
- s_bfe_i64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`
- s_bfe_u32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_bfe_u64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`
- s_bfm_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_bfm_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`::ref:`b32<amdgpu_synid9_type_dev>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`b32<amdgpu_synid9_type_dev>`
- s_cbranch_g_fork :ref:`ssrc0<amdgpu_synid9_ssrc64_2>`, :ref:`ssrc1<amdgpu_synid9_ssrc64_2>`
- s_cselect_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_cselect_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc64_0>`
- s_lshl1_add_u32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_lshl2_add_u32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_lshl3_add_u32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_lshl4_add_u32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_lshl_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`
- s_lshl_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`
- s_lshr_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`
- s_lshr_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`
- s_max_i32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_max_u32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_min_i32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_min_u32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_mul_hi_i32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_mul_hi_u32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_mul_i32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_nand_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_nand_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc64_0>`
- s_nor_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_nor_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc64_0>`
- s_or_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_or_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc64_0>`
- s_orn2_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_orn2_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc64_0>`
- s_pack_hh_b32_b16 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`::ref:`b16x2<amdgpu_synid9_type_dev>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`b16x2<amdgpu_synid9_type_dev>`
- s_pack_lh_b32_b16 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`b16x2<amdgpu_synid9_type_dev>`
- s_pack_ll_b32_b16 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_rfe_restore_b64 :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`b32<amdgpu_synid9_type_dev>`
- s_sub_i32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_sub_u32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_subb_u32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_xnor_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_xnor_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc64_0>`
- s_xor_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_xor_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc64_0>`
+ **INSTRUCTION** **DST** **SRC0** **SRC1**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_abs
diff _i32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_add_i32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_add_u32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_addc_u32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_and_b32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_and_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc_1>`
+ s_andn2_b32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_andn2_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc_1>`
+ s_ashr_i32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`
+ s_ashr_i64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`
+ s_bfe_i32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`
+ s_bfe_i64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`
+ s_bfe_u32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_bfe_u64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`
+ s_bfm_b32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_bfm_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`
+ s_cbranch_g_fork :ref:`ssrc0<amdgpu_synid_gfx9_ssrc_4>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc_4>`
+ s_cselect_b32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_cselect_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc_1>`
+ s_lshl1_add_u32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_lshl2_add_u32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_lshl3_add_u32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_lshl4_add_u32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_lshl_b32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`
+ s_lshl_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`
+ s_lshr_b32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`
+ s_lshr_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`
+ s_max_i32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_max_u32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_min_i32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_min_u32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_mul_hi_i32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_mul_hi_u32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_mul_i32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_nand_b32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_nand_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc_1>`
+ s_nor_b32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_nor_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc_1>`
+ s_or_b32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_or_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc_1>`
+ s_orn2_b32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_orn2_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc_1>`
+ s_pack_hh_b32_b16 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`
+ s_pack_lh_b32_b16 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`
+ s_pack_ll_b32_b16 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_rfe_restore_b64 :ref:`ssrc0<amdgpu_synid_gfx9_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`
+ s_sub_i32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_sub_u32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_subb_u32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_xnor_b32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_xnor_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc_1>`
+ s_xor_b32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_xor_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc_1>`
SOPC
-----------------------
@@ -747,27 +747,27 @@ SOPC
.. parsed-literal::
**INSTRUCTION** **SRC0** **SRC1**
- \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- s_bitcmp0_b32 :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_bitcmp0_b64 :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`
- s_bitcmp1_b32 :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_bitcmp1_b64 :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`
- s_cmp_eq_i32 :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_cmp_eq_u32 :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_cmp_eq_u64 :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc64_0>`
- s_cmp_ge_i32 :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_cmp_ge_u32 :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_cmp_gt_i32 :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_cmp_gt_u32 :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_cmp_le_i32 :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_cmp_le_u32 :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_cmp_lg_i32 :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_cmp_lg_u32 :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_cmp_lg_u64 :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc64_0>`
- s_cmp_lt_i32 :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_cmp_lt_u32 :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
- s_set_gpr_idx_on :ref:`ssrc<amdgpu_synid9_ssrc32_0>`, :ref:`imask<amdgpu_synid9_imask>`
- s_setvskip :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_bitcmp0_b32 :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_bitcmp0_b64 :ref:`ssrc0<amdgpu_synid_gfx9_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`
+ s_bitcmp1_b32 :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_bitcmp1_b64 :ref:`ssrc0<amdgpu_synid_gfx9_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`
+ s_cmp_eq_i32 :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_cmp_eq_u32 :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_cmp_eq_u64 :ref:`ssrc0<amdgpu_synid_gfx9_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc_1>`
+ s_cmp_ge_i32 :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_cmp_ge_u32 :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_cmp_gt_i32 :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_cmp_gt_u32 :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_cmp_le_i32 :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_cmp_le_u32 :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_cmp_lg_i32 :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_cmp_lg_u32 :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_cmp_lg_u64 :ref:`ssrc0<amdgpu_synid_gfx9_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc_1>`
+ s_cmp_lt_i32 :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_cmp_lt_u32 :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
+ s_set_gpr_idx_on :ref:`ssrc<amdgpu_synid_gfx9_ssrc>`, :ref:`imask<amdgpu_synid_gfx9_imask>`
+ s_setvskip :ref:`ssrc0<amdgpu_synid_gfx9_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc>`
SOPK
-----------------------
@@ -775,28 +775,28 @@ SOPK
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1**
- \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- s_addk_i32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`imm16<amdgpu_synid9_simm16>`
- s_call_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`label<amdgpu_synid9_label>`
- s_cbranch_i_fork :ref:`ssrc<amdgpu_synid9_ssrc64_3>`, :ref:`label<amdgpu_synid9_label>`
- s_cmovk_i32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`imm16<amdgpu_synid9_simm16>`
- s_cmpk_eq_i32 :ref:`ssrc<amdgpu_synid9_ssrc32_2>`, :ref:`imm16<amdgpu_synid9_simm16>`
- s_cmpk_eq_u32 :ref:`ssrc<amdgpu_synid9_ssrc32_2>`, :ref:`imm16<amdgpu_synid9_uimm16>`
- s_cmpk_ge_i32 :ref:`ssrc<amdgpu_synid9_ssrc32_2>`, :ref:`imm16<amdgpu_synid9_simm16>`
- s_cmpk_ge_u32 :ref:`ssrc<amdgpu_synid9_ssrc32_2>`, :ref:`imm16<amdgpu_synid9_uimm16>`
- s_cmpk_gt_i32 :ref:`ssrc<amdgpu_synid9_ssrc32_2>`, :ref:`imm16<amdgpu_synid9_simm16>`
- s_cmpk_gt_u32 :ref:`ssrc<amdgpu_synid9_ssrc32_2>`, :ref:`imm16<amdgpu_synid9_uimm16>`
- s_cmpk_le_i32 :ref:`ssrc<amdgpu_synid9_ssrc32_2>`, :ref:`imm16<amdgpu_synid9_simm16>`
- s_cmpk_le_u32 :ref:`ssrc<amdgpu_synid9_ssrc32_2>`, :ref:`imm16<amdgpu_synid9_uimm16>`
- s_cmpk_lg_i32 :ref:`ssrc<amdgpu_synid9_ssrc32_2>`, :ref:`imm16<amdgpu_synid9_simm16>`
- s_cmpk_lg_u32 :ref:`ssrc<amdgpu_synid9_ssrc32_2>`, :ref:`imm16<amdgpu_synid9_uimm16>`
- s_cmpk_lt_i32 :ref:`ssrc<amdgpu_synid9_ssrc32_2>`, :ref:`imm16<amdgpu_synid9_simm16>`
- s_cmpk_lt_u32 :ref:`ssrc<amdgpu_synid9_ssrc32_2>`, :ref:`imm16<amdgpu_synid9_uimm16>`
- s_getreg_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`hwreg<amdgpu_synid9_hwreg>`
- s_movk_i32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`imm16<amdgpu_synid9_simm16>`
- s_mulk_i32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`imm16<amdgpu_synid9_simm16>`
- s_setreg_b32 :ref:`hwreg<amdgpu_synid9_hwreg>`, :ref:`ssrc<amdgpu_synid9_ssrc32_2>`
- s_setreg_imm32_b32 :ref:`hwreg<amdgpu_synid9_hwreg>`, :ref:`imm32<amdgpu_synid9_bimm32>`
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_addk_i32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`imm16<amdgpu_synid_gfx9_imm16>`
+ s_call_b64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`label<amdgpu_synid_gfx9_label>`
+ s_cbranch_i_fork :ref:`ssrc<amdgpu_synid_gfx9_ssrc_5>`, :ref:`label<amdgpu_synid_gfx9_label>`
+ s_cmovk_i32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`imm16<amdgpu_synid_gfx9_imm16>`
+ s_cmpk_eq_i32 :ref:`ssrc<amdgpu_synid_gfx9_ssrc_6>`, :ref:`imm16<amdgpu_synid_gfx9_imm16>`
+ s_cmpk_eq_u32 :ref:`ssrc<amdgpu_synid_gfx9_ssrc_6>`, :ref:`imm16<amdgpu_synid_gfx9_imm16_1>`
+ s_cmpk_ge_i32 :ref:`ssrc<amdgpu_synid_gfx9_ssrc_6>`, :ref:`imm16<amdgpu_synid_gfx9_imm16>`
+ s_cmpk_ge_u32 :ref:`ssrc<amdgpu_synid_gfx9_ssrc_6>`, :ref:`imm16<amdgpu_synid_gfx9_imm16_1>`
+ s_cmpk_gt_i32 :ref:`ssrc<amdgpu_synid_gfx9_ssrc_6>`, :ref:`imm16<amdgpu_synid_gfx9_imm16>`
+ s_cmpk_gt_u32 :ref:`ssrc<amdgpu_synid_gfx9_ssrc_6>`, :ref:`imm16<amdgpu_synid_gfx9_imm16_1>`
+ s_cmpk_le_i32 :ref:`ssrc<amdgpu_synid_gfx9_ssrc_6>`, :ref:`imm16<amdgpu_synid_gfx9_imm16>`
+ s_cmpk_le_u32 :ref:`ssrc<amdgpu_synid_gfx9_ssrc_6>`, :ref:`imm16<amdgpu_synid_gfx9_imm16_1>`
+ s_cmpk_lg_i32 :ref:`ssrc<amdgpu_synid_gfx9_ssrc_6>`, :ref:`imm16<amdgpu_synid_gfx9_imm16>`
+ s_cmpk_lg_u32 :ref:`ssrc<amdgpu_synid_gfx9_ssrc_6>`, :ref:`imm16<amdgpu_synid_gfx9_imm16_1>`
+ s_cmpk_lt_i32 :ref:`ssrc<amdgpu_synid_gfx9_ssrc_6>`, :ref:`imm16<amdgpu_synid_gfx9_imm16>`
+ s_cmpk_lt_u32 :ref:`ssrc<amdgpu_synid_gfx9_ssrc_6>`, :ref:`imm16<amdgpu_synid_gfx9_imm16_1>`
+ s_getreg_b32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`hwreg<amdgpu_synid_gfx9_hwreg>`
+ s_movk_i32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`imm16<amdgpu_synid_gfx9_imm16>`
+ s_mulk_i32 :ref:`sdst<amdgpu_synid_gfx9_sdst_5>`, :ref:`imm16<amdgpu_synid_gfx9_imm16>`
+ s_setreg_b32 :ref:`hwreg<amdgpu_synid_gfx9_hwreg>`, :ref:`ssrc<amdgpu_synid_gfx9_ssrc_6>`
+ s_setreg_imm32_b32 :ref:`hwreg<amdgpu_synid_gfx9_hwreg>`, :ref:`simm32<amdgpu_synid_gfx9_simm32>`
SOPP
-----------------------
@@ -804,37 +804,37 @@ SOPP
.. parsed-literal::
**INSTRUCTION** **SRC**
- \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
s_barrier
- s_branch :ref:`label<amdgpu_synid9_label>`
- s_cbranch_cdbgsys :ref:`label<amdgpu_synid9_label>`
- s_cbranch_cdbgsys_and_user :ref:`label<amdgpu_synid9_label>`
- s_cbranch_cdbgsys_or_user :ref:`label<amdgpu_synid9_label>`
- s_cbranch_cdbguser :ref:`label<amdgpu_synid9_label>`
- s_cbranch_execnz :ref:`label<amdgpu_synid9_label>`
- s_cbranch_execz :ref:`label<amdgpu_synid9_label>`
- s_cbranch_scc0 :ref:`label<amdgpu_synid9_label>`
- s_cbranch_scc1 :ref:`label<amdgpu_synid9_label>`
- s_cbranch_vccnz :ref:`label<amdgpu_synid9_label>`
- s_cbranch_vccz :ref:`label<amdgpu_synid9_label>`
- s_decperflevel :ref:`imm16<amdgpu_synid9_bimm16>`
+ s_branch :ref:`label<amdgpu_synid_gfx9_label>`
+ s_cbranch_cdbgsys :ref:`label<amdgpu_synid_gfx9_label>`
+ s_cbranch_cdbgsys_and_user :ref:`label<amdgpu_synid_gfx9_label>`
+ s_cbranch_cdbgsys_or_user :ref:`label<amdgpu_synid_gfx9_label>`
+ s_cbranch_cdbguser :ref:`label<amdgpu_synid_gfx9_label>`
+ s_cbranch_execnz :ref:`label<amdgpu_synid_gfx9_label>`
+ s_cbranch_execz :ref:`label<amdgpu_synid_gfx9_label>`
+ s_cbranch_scc0 :ref:`label<amdgpu_synid_gfx9_label>`
+ s_cbranch_scc1 :ref:`label<amdgpu_synid_gfx9_label>`
+ s_cbranch_vccnz :ref:`label<amdgpu_synid_gfx9_label>`
+ s_cbranch_vccz :ref:`label<amdgpu_synid_gfx9_label>`
+ s_decperflevel :ref:`imm16<amdgpu_synid_gfx9_imm16_2>`
s_endpgm
s_endpgm_ordered_ps_done
s_endpgm_saved
s_icache_inv
- s_incperflevel :ref:`imm16<amdgpu_synid9_bimm16>`
- s_nop :ref:`imm16<amdgpu_synid9_bimm16>`
- s_sendmsg :ref:`msg<amdgpu_synid9_msg>`
- s_sendmsghalt :ref:`msg<amdgpu_synid9_msg>`
- s_set_gpr_idx_mode :ref:`imask<amdgpu_synid9_imask>`
+ s_incperflevel :ref:`imm16<amdgpu_synid_gfx9_imm16_2>`
+ s_nop :ref:`imm16<amdgpu_synid_gfx9_imm16_2>`
+ s_sendmsg :ref:`msg<amdgpu_synid_gfx9_msg>`
+ s_sendmsghalt :ref:`msg<amdgpu_synid_gfx9_msg>`
+ s_set_gpr_idx_mode :ref:`imask<amdgpu_synid_gfx9_imask>`
s_set_gpr_idx_off
- s_sethalt :ref:`imm16<amdgpu_synid9_bimm16>`
- s_setkill :ref:`imm16<amdgpu_synid9_bimm16>`
- s_setprio :ref:`imm16<amdgpu_synid9_bimm16>`
- s_sleep :ref:`imm16<amdgpu_synid9_bimm16>`
- s_trap :ref:`imm16<amdgpu_synid9_bimm16>`
+ s_sethalt :ref:`imm16<amdgpu_synid_gfx9_imm16_2>`
+ s_setkill :ref:`imm16<amdgpu_synid_gfx9_imm16_2>`
+ s_setprio :ref:`imm16<amdgpu_synid_gfx9_imm16_2>`
+ s_sleep :ref:`imm16<amdgpu_synid_gfx9_imm16_2>`
+ s_trap :ref:`imm16<amdgpu_synid_gfx9_imm16_2>`
s_ttracedata
- s_waitcnt :ref:`waitcnt<amdgpu_synid9_waitcnt>`
+ s_waitcnt :ref:`waitcnt<amdgpu_synid_gfx9_waitcnt>`
s_wakeup
VINTRP
@@ -843,1289 +843,1291 @@ VINTRP
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1**
- \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- v_interp_mov_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`param<amdgpu_synid9_param>`::ref:`b32<amdgpu_synid9_type_dev>`, :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>`
- v_interp_p1_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`, :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>`
- v_interp_p2_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`, :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>`
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_interp_mov_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`param<amdgpu_synid_gfx9_param>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`, :ref:`attr<amdgpu_synid_gfx9_attr>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`
+ v_interp_p1_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`, :ref:`attr<amdgpu_synid_gfx9_attr>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`
+ v_interp_p2_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`, :ref:`attr<amdgpu_synid_gfx9_attr>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`
VOP1
-----------------------
.. parsed-literal::
- **INSTRUCTION** **DST** **SRC** **MODIFIERS**
- \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- v_bfrev_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_bfrev_b32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_bfrev_b32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_ceil_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_ceil_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_ceil_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_ceil_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_ceil_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_ceil_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_ceil_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src64_0>`
+ **INSTRUCTION** **DST** **SRC** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_bfrev_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_bfrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_bfrev_b32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ceil_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_ceil_f16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_ceil_f16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ceil_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_ceil_f32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_ceil_f32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ceil_f64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src<amdgpu_synid_gfx9_src_2>`
v_clrexcp
- v_cos_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_cos_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cos_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cos_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_cos_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cos_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f16_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_cvt_f16_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_f16_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f16_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`
- v_cvt_f16_i16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_f16_i16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f16_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`
- v_cvt_f16_u16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_f16_u16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f32_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_cvt_f32_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_f32_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f32_f64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src64_0>`
- v_cvt_f32_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_cvt_f32_i32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_f32_i32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f32_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_cvt_f32_u32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_f32_u32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f32_ubyte0 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_cvt_f32_ubyte0_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_f32_ubyte0_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f32_ubyte1 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_cvt_f32_ubyte1_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_f32_ubyte1_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f32_ubyte2 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_cvt_f32_ubyte2_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_f32_ubyte2_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f32_ubyte3 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_cvt_f32_ubyte3_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_f32_ubyte3_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f64_f32 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_cvt_f64_i32 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_cvt_f64_u32 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_cvt_flr_i32_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_cvt_flr_i32_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_flr_i32_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_i16_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_cvt_i16_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_i16_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_i32_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_cvt_i32_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_i32_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_i32_f64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src64_0>`
- v_cvt_norm_i16_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_cvt_norm_i16_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_norm_i16_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_norm_u16_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_cvt_norm_u16_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_norm_u16_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_off_f32_i4 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_cvt_off_f32_i4_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_off_f32_i4_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_rpi_i32_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_cvt_rpi_i32_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_rpi_i32_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_u16_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_cvt_u16_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_u16_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_u32_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_cvt_u32_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cvt_u32_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_u32_f64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src64_0>`
- v_exp_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_exp_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_exp_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_exp_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_exp_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_exp_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_exp_legacy_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_exp_legacy_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_exp_legacy_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_ffbh_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_ffbh_i32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_ffbh_i32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_ffbh_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_ffbh_u32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_ffbh_u32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_ffbl_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_ffbl_b32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_ffbl_b32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_floor_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_floor_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_floor_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_floor_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_floor_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_floor_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_floor_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src64_0>`
- v_fract_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_fract_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_fract_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_fract_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_fract_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_fract_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_fract_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src64_0>`
- v_frexp_exp_i16_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_frexp_exp_i16_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_frexp_exp_i16_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_frexp_exp_i32_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_frexp_exp_i32_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_frexp_exp_i32_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_frexp_exp_i32_f64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src64_0>`
- v_frexp_mant_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_frexp_mant_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_frexp_mant_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_frexp_mant_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_frexp_mant_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_frexp_mant_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_frexp_mant_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src64_0>`
- v_log_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_log_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_log_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_log_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_log_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_log_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_log_legacy_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_log_legacy_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_log_legacy_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_mov_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_mov_b32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_mov_b32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cos_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_cos_f16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cos_f16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cos_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_cos_f32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cos_f32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f16_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_cvt_f16_f32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_f16_f32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f16_i16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_3>`
+ v_cvt_f16_i16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_f16_i16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f16_u16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_3>`
+ v_cvt_f16_u16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_f16_u16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_cvt_f32_f16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_f32_f16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_f64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_2>`
+ v_cvt_f32_i32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_cvt_f32_i32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_f32_i32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_cvt_f32_u32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_f32_u32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_ubyte0 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_cvt_f32_ubyte0_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_f32_ubyte0_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_ubyte1 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_cvt_f32_ubyte1_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_f32_ubyte1_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_ubyte2 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_cvt_f32_ubyte2_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_f32_ubyte2_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_ubyte3 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_cvt_f32_ubyte3_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_f32_ubyte3_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f64_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_cvt_f64_i32 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_cvt_f64_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_cvt_flr_i32_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_cvt_flr_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_flr_i32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_i16_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_cvt_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_i16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_i32_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_cvt_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_i32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_i32_f64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_2>`
+ v_cvt_norm_i16_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_cvt_norm_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_norm_i16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_norm_u16_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_cvt_norm_u16_f16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_norm_u16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_off_f32_i4 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_cvt_off_f32_i4_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_off_f32_i4_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_rpi_i32_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_cvt_rpi_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_rpi_i32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_u16_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_cvt_u16_f16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_u16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_u32_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_cvt_u32_f32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_u32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_u32_f64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_2>`
+ v_exp_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_exp_f16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_exp_f16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_exp_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_exp_f32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_exp_f32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_exp_legacy_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_exp_legacy_f32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_exp_legacy_f32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ffbh_i32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_ffbh_i32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_ffbh_i32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ffbh_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_ffbh_u32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_ffbh_u32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ffbl_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_ffbl_b32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_ffbl_b32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_floor_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_floor_f16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_floor_f16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_floor_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_floor_f32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_floor_f32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_floor_f64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src<amdgpu_synid_gfx9_src_2>`
+ v_fract_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_fract_f16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_fract_f16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_fract_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_fract_f32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_fract_f32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_fract_f64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src<amdgpu_synid_gfx9_src_2>`
+ v_frexp_exp_i16_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_frexp_exp_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_frexp_exp_i16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_frexp_exp_i32_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_frexp_exp_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_frexp_exp_i32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_frexp_exp_i32_f64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_2>`
+ v_frexp_mant_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_frexp_mant_f16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_frexp_mant_f16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_frexp_mant_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_frexp_mant_f32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_frexp_mant_f32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_frexp_mant_f64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src<amdgpu_synid_gfx9_src_2>`
+ v_log_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_log_f16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_log_f16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_log_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_log_f32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_log_f32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_log_legacy_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_log_legacy_f32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_log_legacy_f32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_mov_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_mov_b32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_mov_b32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
v_nop
- v_not_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_not_b32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_not_b32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_rcp_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_rcp_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_rcp_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_rcp_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_rcp_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_rcp_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_rcp_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src64_0>`
- v_rcp_iflag_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_rcp_iflag_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_rcp_iflag_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_readfirstlane_b32 :ref:`sdst<amdgpu_synid9_sdst32_2>`, :ref:`vsrc<amdgpu_synid9_vsrc32_1>`
- v_rndne_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_rndne_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_rndne_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_rndne_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_rndne_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_rndne_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_rndne_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src64_0>`
- v_rsq_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_rsq_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_rsq_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_rsq_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_rsq_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_rsq_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_rsq_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src64_0>`
- v_sat_pk_u8_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_sat_pk_u8_i16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_sat_pk_u8_i16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_screen_partition_4se_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_screen_partition_4se_b32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_screen_partition_4se_b32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_sin_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_sin_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_sin_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_sin_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_sin_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_sin_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_sqrt_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_sqrt_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_sqrt_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_sqrt_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_sqrt_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_sqrt_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_sqrt_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src64_0>`
- v_swap_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`
- v_trunc_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_trunc_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_trunc_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_trunc_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
- v_trunc_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_trunc_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_trunc_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src64_0>`
+ v_not_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_not_b32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_not_b32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rcp_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_rcp_f16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_rcp_f16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rcp_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_rcp_f32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_rcp_f32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rcp_f64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src<amdgpu_synid_gfx9_src_2>`
+ v_rcp_iflag_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_rcp_iflag_f32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_rcp_iflag_f32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_readfirstlane_b32 :ref:`sdst<amdgpu_synid_gfx9_sdst_7>`, :ref:`src<amdgpu_synid_gfx9_src_5>`
+ v_rndne_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_rndne_f16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_rndne_f16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rndne_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_rndne_f32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_rndne_f32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rndne_f64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src<amdgpu_synid_gfx9_src_2>`
+ v_rsq_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_rsq_f16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_rsq_f16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rsq_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_rsq_f32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_rsq_f32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rsq_f64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src<amdgpu_synid_gfx9_src_2>`
+ v_sat_pk_u8_i16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`::ref:`u8x4<amdgpu_synid_gfx9_type_deviation>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_sat_pk_u8_i16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`::ref:`u8x4<amdgpu_synid_gfx9_type_deviation>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_sat_pk_u8_i16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`::ref:`u8x4<amdgpu_synid_gfx9_type_deviation>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_screen_partition_4se_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_screen_partition_4se_b32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_screen_partition_4se_b32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sin_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_sin_f16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_sin_f16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sin_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_sin_f32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_sin_f32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sqrt_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_sqrt_f16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_sqrt_f16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sqrt_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_sqrt_f32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_sqrt_f32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sqrt_f64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src<amdgpu_synid_gfx9_src_2>`
+ v_swap_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`
+ v_trunc_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_trunc_f16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_trunc_f16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_trunc_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src>`
+ v_trunc_f32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_trunc_f32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_trunc_f64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src<amdgpu_synid_gfx9_src_2>`
VOP2
-----------------------
.. parsed-literal::
- **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS**
- \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- v_add_co_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_add_co_u32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_add_co_u32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_add_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_add_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_add_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_add_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_add_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_add_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_add_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_add_u16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_add_u16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_add_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_add_u32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_add_u32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_addc_co_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`
- v_addc_co_u32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_addc_co_u32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vcc<amdgpu_synid9_vcc_64>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_and_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_and_b32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_and_b32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_ashrrev_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_ashrrev_i16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_ashrrev_i16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_ashrrev_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_ashrrev_i32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_ashrrev_i32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cndmask_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`
- v_cndmask_b32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_cndmask_b32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vcc<amdgpu_synid9_vcc_64>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_ldexp_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`i16<amdgpu_synid9_type_dev>`
- v_ldexp_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`i16<amdgpu_synid9_type_dev>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_ldexp_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`i16<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_lshlrev_b16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_lshlrev_b16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_lshlrev_b16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_lshlrev_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_lshlrev_b32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_lshlrev_b32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_lshrrev_b16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_lshrrev_b16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_lshrrev_b16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_lshrrev_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_lshrrev_b32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_lshrrev_b32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mac_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_mac_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_mac_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_mac_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_madak_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`, :ref:`imm32<amdgpu_synid9_fimm16>`
- v_madak_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`, :ref:`imm32<amdgpu_synid9_fimm32>`
- v_madmk_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`imm32<amdgpu_synid9_fimm16>`, :ref:`vsrc2<amdgpu_synid9_vsrc32_0>`
- v_madmk_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`imm32<amdgpu_synid9_fimm32>`, :ref:`vsrc2<amdgpu_synid9_vsrc32_0>`
- v_max_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_max_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_max_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_max_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_max_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_max_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_max_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_max_i16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_max_i16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_max_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_max_i32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_max_i32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_max_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_max_u16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_max_u16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_max_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_max_u32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_max_u32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_min_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_min_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_min_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_min_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_min_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_min_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_min_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_min_i16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_min_i16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_min_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_min_i32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_min_i32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_min_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_min_u16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_min_u16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_min_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_min_u32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_min_u32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mul_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_mul_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_mul_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mul_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_mul_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_mul_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mul_hi_i32_i24 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_mul_hi_i32_i24_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_mul_hi_i32_i24_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mul_hi_u32_u24 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_mul_hi_u32_u24_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_mul_hi_u32_u24_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mul_i32_i24 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_mul_i32_i24_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_mul_i32_i24_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mul_legacy_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_mul_legacy_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_mul_legacy_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mul_lo_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_mul_lo_u16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_mul_lo_u16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mul_u32_u24 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_mul_u32_u24_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_mul_u32_u24_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_or_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_or_b32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_or_b32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_sub_co_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_sub_co_u32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_sub_co_u32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_sub_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_sub_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_sub_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_sub_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_sub_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_sub_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_sub_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_sub_u16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_sub_u16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_sub_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_sub_u32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_sub_u32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subb_co_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`
- v_subb_co_u32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_subb_co_u32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vcc<amdgpu_synid9_vcc_64>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subbrev_co_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_3>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`
- v_subbrev_co_u32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_subbrev_co_u32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vcc<amdgpu_synid9_vcc_64>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subrev_co_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_3>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_subrev_co_u32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_subrev_co_u32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subrev_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_3>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_subrev_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_subrev_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subrev_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_3>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_subrev_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_subrev_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subrev_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_subrev_u16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_subrev_u16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subrev_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_3>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_subrev_u32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_subrev_u32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_xor_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_xor_b32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_xor_b32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_add_co_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_add_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_add_co_u32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_add_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_add_f16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_add_f16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_add_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_add_f32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_add_f32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_add_u16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_add_u16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_add_u16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_add_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_add_u32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_add_u32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_addc_co_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vcc<amdgpu_synid_gfx9_vcc>`
+ v_addc_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vcc<amdgpu_synid_gfx9_vcc>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_addc_co_u32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`vcc<amdgpu_synid_gfx9_vcc>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_and_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_and_b32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_and_b32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_ashrrev_i16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_6>`::ref:`u16<amdgpu_synid_gfx9_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_ashrrev_i16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`::ref:`u16<amdgpu_synid_gfx9_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_ashrrev_i16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`::ref:`u16<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_ashrrev_i32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_7>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_ashrrev_i32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_ashrrev_i32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cndmask_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vcc<amdgpu_synid_gfx9_vcc>`
+ v_cndmask_b32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vcc<amdgpu_synid_gfx9_vcc>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cndmask_b32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`vcc<amdgpu_synid_gfx9_vcc>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_ldexp_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`::ref:`i16<amdgpu_synid_gfx9_type_deviation>`
+ v_ldexp_f16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`::ref:`i16<amdgpu_synid_gfx9_type_deviation>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_ldexp_f16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`::ref:`i16<amdgpu_synid_gfx9_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_lshlrev_b16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_6>`::ref:`u16<amdgpu_synid_gfx9_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_lshlrev_b16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`::ref:`u16<amdgpu_synid_gfx9_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_lshlrev_b16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`::ref:`u16<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_lshlrev_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_7>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_lshlrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_lshlrev_b32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_lshrrev_b16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_6>`::ref:`u16<amdgpu_synid_gfx9_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_lshrrev_b16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`::ref:`u16<amdgpu_synid_gfx9_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_lshrrev_b16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`::ref:`u16<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_lshrrev_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_7>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_lshrrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_lshrrev_b32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mac_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_mac_f16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_mac_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_mac_f32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_madak_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`, :ref:`simm32<amdgpu_synid_gfx9_simm32_1>`
+ v_madak_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`, :ref:`simm32<amdgpu_synid_gfx9_simm32_2>`
+ v_madmk_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`simm32<amdgpu_synid_gfx9_simm32_1>`, :ref:`vsrc2<amdgpu_synid_gfx9_vsrc_1>`
+ v_madmk_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`simm32<amdgpu_synid_gfx9_simm32_2>`, :ref:`vsrc2<amdgpu_synid_gfx9_vsrc_1>`
+ v_max_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_max_f16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_max_f16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_max_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_max_f32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_max_f32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_max_i16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_max_i16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_max_i16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_max_i32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_max_i32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_max_i32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_max_u16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_max_u16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_max_u16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_max_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_max_u32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_max_u32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_min_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_min_f16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_min_f16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_min_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_min_f32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_min_f32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_min_i16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_min_i16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_min_i16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_min_i32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_min_i32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_min_i32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_min_u16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_min_u16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_min_u16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_min_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_min_u32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_min_u32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_mul_f16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_mul_f16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_mul_f32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_mul_f32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_hi_i32_i24 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_mul_hi_i32_i24_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_mul_hi_i32_i24_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_hi_u32_u24 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_mul_hi_u32_u24_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_mul_hi_u32_u24_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_i32_i24 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_mul_i32_i24_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_mul_i32_i24_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_legacy_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_mul_legacy_f32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_mul_legacy_f32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_lo_u16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_mul_lo_u16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_mul_lo_u16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_u32_u24 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_mul_u32_u24_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_mul_u32_u24_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_or_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_or_b32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_or_b32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_sub_co_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_sub_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_sub_co_u32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_sub_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_sub_f16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_sub_f16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_sub_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_sub_f32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_sub_f32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_sub_u16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_sub_u16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_sub_u16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_sub_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_sub_u32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_sub_u32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subb_co_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vcc<amdgpu_synid_gfx9_vcc>`
+ v_subb_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vcc<amdgpu_synid_gfx9_vcc>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_subb_co_u32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`vcc<amdgpu_synid_gfx9_vcc>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subbrev_co_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_7>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vcc<amdgpu_synid_gfx9_vcc>`
+ v_subbrev_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vcc<amdgpu_synid_gfx9_vcc>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_subbrev_co_u32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`vcc<amdgpu_synid_gfx9_vcc>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_co_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_7>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_subrev_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_subrev_co_u32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_7>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_subrev_f16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_subrev_f16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_7>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_subrev_f32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_subrev_f32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_u16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_6>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_subrev_u16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_subrev_u16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_7>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_subrev_u32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_subrev_u32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_xor_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_xor_b32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_xor_b32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
VOP3
-----------------------
.. parsed-literal::
- **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS**
- \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- v_add3_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`, :ref:`src2<amdgpu_synid9_src32_5>`
- v_add_co_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>` :ref:`clamp<amdgpu_synid_clamp>`
- v_add_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_add_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_add_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_add_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_add_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>` :ref:`clamp<amdgpu_synid_clamp>`
- v_add_lshl_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`, :ref:`src2<amdgpu_synid9_src32_5>`
- v_add_u16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>` :ref:`clamp<amdgpu_synid_clamp>`
- v_add_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>` :ref:`clamp<amdgpu_synid_clamp>`
- v_addc_co_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`, :ref:`ssrc2<amdgpu_synid9_ssrc64_1>` :ref:`clamp<amdgpu_synid_clamp>`
- v_alignbit_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`, :ref:`src2<amdgpu_synid9_src32_5>`
- v_alignbyte_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`, :ref:`src2<amdgpu_synid9_src32_5>`
- v_and_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_and_or_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`, :ref:`src2<amdgpu_synid9_src32_5>`
- v_ashrrev_i16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_7>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_ashrrev_i32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_ashrrev_i64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src0<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_bcnt_u32_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_bfe_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>`
- v_bfe_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`, :ref:`src2<amdgpu_synid9_src32_5>`
- v_bfi_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`, :ref:`src2<amdgpu_synid9_src32_5>`
- v_bfm_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_bfrev_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`
- v_ceil_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_ceil_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_ceil_f64_e64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_add3_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`
+ v_add_co_u32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_f16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_f32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_add_f64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_add_i16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_i32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_lshl_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`
+ v_add_u16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_u32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_addc_co_u32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`, :ref:`ssrc2<amdgpu_synid_gfx9_ssrc_3>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_alignbit_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`, :ref:`src2<amdgpu_synid_gfx9_src_4>`::ref:`b16<amdgpu_synid_gfx9_type_deviation>`
+ v_alignbyte_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`, :ref:`src2<amdgpu_synid_gfx9_src_4>`::ref:`b16<amdgpu_synid_gfx9_type_deviation>`
+ v_and_b32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_and_or_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`
+ v_ashrrev_i16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`u16<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_ashrrev_i32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_ashrrev_i64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_bcnt_u32_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_bfe_i32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`
+ v_bfe_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`
+ v_bfi_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`
+ v_bfm_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_bfrev_b32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`
+ v_ceil_f16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_ceil_f32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ceil_f64_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_clrexcp_e64
- v_cmp_class_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`b32<amdgpu_synid9_type_dev>`
- v_cmp_class_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`b32<amdgpu_synid9_type_dev>`
- v_cmp_class_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`b32<amdgpu_synid9_type_dev>`
- v_cmp_eq_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_eq_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_eq_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_eq_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_cmp_eq_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_cmp_eq_i64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmp_eq_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_cmp_eq_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_cmp_eq_u64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmp_f_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_f_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_f_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_f_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_cmp_f_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_cmp_f_i64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmp_f_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_cmp_f_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_cmp_f_u64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmp_ge_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_ge_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_ge_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_ge_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_cmp_ge_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_cmp_ge_i64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmp_ge_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_cmp_ge_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_cmp_ge_u64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmp_gt_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_gt_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_gt_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_gt_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_cmp_gt_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_cmp_gt_i64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmp_gt_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_cmp_gt_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_cmp_gt_u64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmp_le_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_le_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_le_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_le_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_cmp_le_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_cmp_le_i64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmp_le_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_cmp_le_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_cmp_le_u64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmp_lg_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_lg_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_lg_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_lt_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_lt_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_lt_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_lt_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_cmp_lt_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_cmp_lt_i64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmp_lt_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_cmp_lt_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_cmp_lt_u64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmp_ne_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_cmp_ne_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_cmp_ne_i64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmp_ne_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_cmp_ne_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_cmp_ne_u64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmp_neq_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_neq_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_neq_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nge_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nge_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nge_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_ngt_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_ngt_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_ngt_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nle_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nle_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nle_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nlg_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nlg_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nlg_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nlt_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nlt_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nlt_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_o_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_o_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_o_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_t_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_cmp_t_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_cmp_t_i64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmp_t_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_cmp_t_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_cmp_t_u64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmp_tru_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_tru_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_tru_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_u_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_u_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_u_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_class_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`b32<amdgpu_synid9_type_dev>`
- v_cmpx_class_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`b32<amdgpu_synid9_type_dev>`
- v_cmpx_class_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`b32<amdgpu_synid9_type_dev>`
- v_cmpx_eq_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_eq_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_eq_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_eq_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_cmpx_eq_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_cmpx_eq_i64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmpx_eq_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_cmpx_eq_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_cmpx_eq_u64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmpx_f_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_f_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_f_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_f_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_cmpx_f_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_cmpx_f_i64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmpx_f_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_cmpx_f_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_cmpx_f_u64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmpx_ge_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_ge_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_ge_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_ge_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_cmpx_ge_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_cmpx_ge_i64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmpx_ge_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_cmpx_ge_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_cmpx_ge_u64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmpx_gt_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_gt_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_gt_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_gt_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_cmpx_gt_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_cmpx_gt_i64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmpx_gt_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_cmpx_gt_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_cmpx_gt_u64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmpx_le_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_le_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_le_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_le_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_cmpx_le_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_cmpx_le_i64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmpx_le_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_cmpx_le_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_cmpx_le_u64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmpx_lg_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_lg_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_lg_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_lt_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_lt_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_lt_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_lt_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_cmpx_lt_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_cmpx_lt_i64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmpx_lt_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_cmpx_lt_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_cmpx_lt_u64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmpx_ne_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_cmpx_ne_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_cmpx_ne_i64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmpx_ne_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_cmpx_ne_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_cmpx_ne_u64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmpx_neq_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_neq_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_neq_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nge_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nge_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nge_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_ngt_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_ngt_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_ngt_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nle_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nle_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nle_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nlg_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nlg_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nlg_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nlt_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nlt_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nlt_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_o_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_o_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_o_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_t_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_cmpx_t_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_cmpx_t_i64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmpx_t_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_cmpx_t_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_cmpx_t_u64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmpx_tru_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_tru_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_tru_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_u_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_u_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_u_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cndmask_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`, :ref:`ssrc2<amdgpu_synid9_ssrc64_1>`
- v_cos_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cos_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cubeid_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cubema_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cubesc_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cubetc_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f16_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f16_i16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_6>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cvt_f16_u16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_6>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cvt_f32_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_f64_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_i32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_ubyte0_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_ubyte1_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_ubyte2_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_ubyte3_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f64_f32_e64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f64_i32_e64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src32_4>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f64_u32_e64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src32_4>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_flr_i32_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
- v_cvt_i16_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cvt_i32_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cvt_i32_f64_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cvt_norm_i16_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cvt_norm_u16_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cvt_off_f32_i4_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_pk_i16_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_cvt_pk_u16_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_cvt_pk_u8_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>`
- v_cvt_pkaccum_u8_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>`
- v_cvt_pknorm_i16_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
- v_cvt_pknorm_i16_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
- v_cvt_pknorm_u16_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
- v_cvt_pknorm_u16_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
- v_cvt_pkrtz_f16_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
- v_cvt_rpi_i32_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
- v_cvt_u16_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cvt_u32_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cvt_u32_f64_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_div_fixup_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_div_fixup_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_div_fixup_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_div_fixup_legacy_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_div_fmas_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_div_fmas_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_div_scale_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`, :ref:`src2<amdgpu_synid9_src32_5>`
- v_div_scale_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`, :ref:`src2<amdgpu_synid9_src64_1>`
- v_exp_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_exp_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_exp_legacy_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_ffbh_i32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`
- v_ffbh_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`
- v_ffbl_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`
- v_floor_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_floor_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_floor_f64_e64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_fma_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_fma_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_fma_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_fma_legacy_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_fract_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_fract_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_fract_f64_e64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_frexp_exp_i16_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
- v_frexp_exp_i32_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
- v_frexp_exp_i32_f64_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
- v_frexp_mant_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_frexp_mant_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_frexp_mant_f64_e64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_interp_mov_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`param<amdgpu_synid9_param>`::ref:`b32<amdgpu_synid9_type_dev>`, :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_interp_p1_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_interp_p1ll_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`f32<amdgpu_synid9_type_dev>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid9_type_dev>`, :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>` :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_interp_p1lv_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`f32<amdgpu_synid9_type_dev>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid9_type_dev>`, :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>`, :ref:`vsrc2<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`::ref:`f16x2<amdgpu_synid9_type_dev>` :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_interp_p2_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid9_type_dev>`, :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>`, :ref:`vsrc2<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid9_type_dev>` :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>`
- v_interp_p2_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_interp_p2_legacy_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid9_type_dev>`, :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>`, :ref:`vsrc2<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid9_type_dev>` :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>`
- v_ldexp_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`i16<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_ldexp_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`i32<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_ldexp_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`i32<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_lerp_u8 :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`b32<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`b32<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src32_5>`::ref:`b32<amdgpu_synid9_type_dev>`
- v_log_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_log_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_log_legacy_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_lshl_add_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`, :ref:`src2<amdgpu_synid9_src32_5>`
- v_lshl_or_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src32_5>`
- v_lshlrev_b16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_7>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_lshlrev_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_lshlrev_b64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src0<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_lshrrev_b16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_7>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_lshrrev_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_lshrrev_b64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src0<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_mac_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mac_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`, :ref:`src2<amdgpu_synid9_src32_7>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_i32_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`, :ref:`src2<amdgpu_synid9_src32_5>`::ref:`i32<amdgpu_synid9_type_dev>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_i32_i24 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`, :ref:`src2<amdgpu_synid9_src32_5>`::ref:`i32<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_i64_i32 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`, :ref:`src2<amdgpu_synid9_src64_1>`::ref:`i64<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_legacy_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_legacy_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_legacy_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`, :ref:`src2<amdgpu_synid9_src32_7>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_legacy_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`, :ref:`src2<amdgpu_synid9_src32_7>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`, :ref:`src2<amdgpu_synid9_src32_7>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_u32_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`, :ref:`src2<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_u32_u24 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`, :ref:`src2<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_u64_u32 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`, :ref:`src2<amdgpu_synid9_src64_1>`::ref:`u64<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_max3_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_max3_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_max3_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`, :ref:`src2<amdgpu_synid9_src32_7>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
- v_max3_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`, :ref:`src2<amdgpu_synid9_src32_5>`
- v_max3_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`, :ref:`src2<amdgpu_synid9_src32_7>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
- v_max3_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`, :ref:`src2<amdgpu_synid9_src32_5>`
- v_max_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_max_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_max_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_max_i16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_max_i32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_max_u16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_max_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_mbcnt_hi_u32_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_mbcnt_lo_u32_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_med3_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_med3_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_med3_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`, :ref:`src2<amdgpu_synid9_src32_7>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
- v_med3_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`, :ref:`src2<amdgpu_synid9_src32_5>`
- v_med3_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`, :ref:`src2<amdgpu_synid9_src32_7>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
- v_med3_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`, :ref:`src2<amdgpu_synid9_src32_5>`
- v_min3_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_min3_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_min3_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`, :ref:`src2<amdgpu_synid9_src32_7>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
- v_min3_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`, :ref:`src2<amdgpu_synid9_src32_5>`
- v_min3_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`, :ref:`src2<amdgpu_synid9_src32_7>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
- v_min3_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`, :ref:`src2<amdgpu_synid9_src32_5>`
- v_min_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_min_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_min_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_min_i16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_min_i32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_min_u16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_min_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_mov_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`
- v_mqsad_pk_u16_u8 :ref:`vdst<amdgpu_synid9_vdst64_0>`::ref:`b64<amdgpu_synid9_type_dev>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`b32<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mqsad_u32_u8 :ref:`vdst<amdgpu_synid9_vdst128_0>`::ref:`b128<amdgpu_synid9_type_dev>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`b32<amdgpu_synid9_type_dev>`, :ref:`vsrc2<amdgpu_synid9_vsrc128_0>`::ref:`b128<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_msad_u8 :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`b32<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`b32<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src32_5>`::ref:`b32<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mul_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mul_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mul_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mul_hi_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_mul_hi_i32_i24_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_mul_hi_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_mul_hi_u32_u24_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_mul_i32_i24_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mul_legacy_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mul_lo_u16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`
- v_mul_lo_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_mul_u32_u24_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_class_f16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`
+ v_cmp_class_f32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`
+ v_cmp_class_f64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`
+ v_cmp_eq_f16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_eq_f32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_eq_f64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_eq_i16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_cmp_eq_i32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_cmp_eq_i64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_cmp_eq_u16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_cmp_eq_u32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_cmp_eq_u64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_cmp_f_f16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_f_f32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_f_f64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_f_i16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_cmp_f_i32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_cmp_f_i64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_cmp_f_u16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_cmp_f_u32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_cmp_f_u64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_cmp_ge_f16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ge_f32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ge_f64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ge_i16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_cmp_ge_i32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_cmp_ge_i64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_cmp_ge_u16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_cmp_ge_u32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_cmp_ge_u64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_cmp_gt_f16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_gt_f32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_gt_f64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_gt_i16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_cmp_gt_i32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_cmp_gt_i64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_cmp_gt_u16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_cmp_gt_u32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_cmp_gt_u64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_cmp_le_f16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_le_f32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_le_f64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_le_i16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_cmp_le_i32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_cmp_le_i64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_cmp_le_u16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_cmp_le_u32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_cmp_le_u64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_cmp_lg_f16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lg_f32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lg_f64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lt_f16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lt_f32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lt_f64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lt_i16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_cmp_lt_i32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_cmp_lt_i64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_cmp_lt_u16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_cmp_lt_u32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_cmp_lt_u64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_cmp_ne_i16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_cmp_ne_i32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_cmp_ne_i64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_cmp_ne_u16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_cmp_ne_u32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_cmp_ne_u64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_cmp_neq_f16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_neq_f32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_neq_f64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nge_f16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nge_f32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nge_f64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ngt_f16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ngt_f32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ngt_f64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nle_f16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nle_f32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nle_f64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlg_f16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlg_f32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlg_f64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlt_f16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlt_f32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlt_f64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_o_f16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_o_f32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_o_f64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_t_i16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_cmp_t_i32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_cmp_t_i64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_cmp_t_u16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_cmp_t_u32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_cmp_t_u64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_cmp_tru_f16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_tru_f32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_tru_f64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_u_f16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_u_f32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_u_f64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_class_f16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`
+ v_cmpx_class_f32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`
+ v_cmpx_class_f64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`
+ v_cmpx_eq_f16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_eq_f32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_eq_f64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_eq_i16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_cmpx_eq_i32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_cmpx_eq_i64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_cmpx_eq_u16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_cmpx_eq_u32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_cmpx_eq_u64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_cmpx_f_f16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_f_f32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_f_f64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_f_i16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_cmpx_f_i32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_cmpx_f_i64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_cmpx_f_u16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_cmpx_f_u32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_cmpx_f_u64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_cmpx_ge_f16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ge_f32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ge_f64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ge_i16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_cmpx_ge_i32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_cmpx_ge_i64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_cmpx_ge_u16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_cmpx_ge_u32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_cmpx_ge_u64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_cmpx_gt_f16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_gt_f32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_gt_f64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_gt_i16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_cmpx_gt_i32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_cmpx_gt_i64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_cmpx_gt_u16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_cmpx_gt_u32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_cmpx_gt_u64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_cmpx_le_f16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_le_f32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_le_f64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_le_i16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_cmpx_le_i32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_cmpx_le_i64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_cmpx_le_u16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_cmpx_le_u32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_cmpx_le_u64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_cmpx_lg_f16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lg_f32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lg_f64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lt_f16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lt_f32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lt_f64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lt_i16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_cmpx_lt_i32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_cmpx_lt_i64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_cmpx_lt_u16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_cmpx_lt_u32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_cmpx_lt_u64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_cmpx_ne_i16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_cmpx_ne_i32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_cmpx_ne_i64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_cmpx_ne_u16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_cmpx_ne_u32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_cmpx_ne_u64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_cmpx_neq_f16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_neq_f32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_neq_f64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nge_f16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nge_f32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nge_f64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ngt_f16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ngt_f32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ngt_f64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nle_f16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nle_f32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nle_f64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlg_f16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlg_f32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlg_f64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlt_f16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlt_f32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlt_f64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_o_f16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_o_f32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_o_f64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_t_i16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_cmpx_t_i32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_cmpx_t_i64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_cmpx_t_u16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_cmpx_t_u32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_cmpx_t_u64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_cmpx_tru_f16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_tru_f32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_tru_f64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_u_f16_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_u_f32_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_u_f64_e64 :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cndmask_b32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`, :ref:`ssrc2<amdgpu_synid_gfx9_ssrc_3>`
+ v_cos_f16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cos_f32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubeid_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubema_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubesc_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubetc_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f16_f32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f16_i16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_10>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_f16_u16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_10>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_f32_f16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_f64_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_i32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_u32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte0_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte1_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte2_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte3_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f64_f32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f64_i32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src<amdgpu_synid_gfx9_src_8>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f64_u32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src<amdgpu_synid_gfx9_src_8>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_flr_i32_f32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`
+ v_cvt_i16_f16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_i32_f32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_i32_f64_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_norm_i16_f16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_norm_u16_f16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_off_f32_i4_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_pk_i16_i32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`i32<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`i32<amdgpu_synid_gfx9_type_deviation>`
+ v_cvt_pk_u16_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`
+ v_cvt_pk_u8_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`::ref:`f32<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`
+ v_cvt_pkaccum_u8_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`::ref:`f32<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`
+ v_cvt_pknorm_i16_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`::ref:`f16<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`::ref:`f16<amdgpu_synid_gfx9_type_deviation>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_cvt_pknorm_i16_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`::ref:`f32<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`::ref:`f32<amdgpu_synid_gfx9_type_deviation>`
+ v_cvt_pknorm_u16_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`::ref:`f16<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`::ref:`f16<amdgpu_synid_gfx9_type_deviation>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_cvt_pknorm_u16_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`::ref:`f32<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`::ref:`f32<amdgpu_synid_gfx9_type_deviation>`
+ v_cvt_pkrtz_f16_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`::ref:`f32<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`::ref:`f32<amdgpu_synid_gfx9_type_deviation>`
+ v_cvt_rpi_i32_f32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`
+ v_cvt_u16_f16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_u32_f32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_u32_f64_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_div_fixup_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_div_fixup_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_fixup_f64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src2<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_fixup_legacy_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_div_fmas_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_fmas_f64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src2<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_scale_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`
+ v_div_scale_f64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`, :ref:`src2<amdgpu_synid_gfx9_src_9>`
+ v_exp_f16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_exp_f32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_exp_legacy_f32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ffbh_i32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`
+ v_ffbh_u32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`
+ v_ffbl_b32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`
+ v_floor_f16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_floor_f32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_floor_f64_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fma_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fma_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fma_f64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src2<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fma_legacy_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fract_f16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fract_f32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fract_f64_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_frexp_exp_i16_f16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`
+ v_frexp_exp_i32_f32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`
+ v_frexp_exp_i32_f64_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`
+ v_frexp_mant_f16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_frexp_mant_f32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_frexp_mant_f64_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_interp_mov_f32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`param<amdgpu_synid_gfx9_param>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`, :ref:`attr<amdgpu_synid_gfx9_attr>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_interp_p1_f32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`attr<amdgpu_synid_gfx9_attr>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_interp_p1ll_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`::ref:`f32<amdgpu_synid_gfx9_type_deviation>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`::ref:`f32<amdgpu_synid_gfx9_type_deviation>`, :ref:`attr<amdgpu_synid_gfx9_attr>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>` :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_interp_p1lv_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`::ref:`f32<amdgpu_synid_gfx9_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`::ref:`f32<amdgpu_synid_gfx9_type_deviation>`, :ref:`attr<amdgpu_synid_gfx9_attr>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`::ref:`f16x2<amdgpu_synid_gfx9_type_deviation>` :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_interp_p2_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`::ref:`f32<amdgpu_synid_gfx9_type_deviation>`, :ref:`attr<amdgpu_synid_gfx9_attr>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`::ref:`f32<amdgpu_synid_gfx9_type_deviation>` :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_interp_p2_f32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`attr<amdgpu_synid_gfx9_attr>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_interp_p2_legacy_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`::ref:`f32<amdgpu_synid_gfx9_type_deviation>`, :ref:`attr<amdgpu_synid_gfx9_attr>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx9_vsrc_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`::ref:`f32<amdgpu_synid_gfx9_type_deviation>` :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_ldexp_f16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`i16<amdgpu_synid_gfx9_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_ldexp_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`i32<amdgpu_synid_gfx9_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ldexp_f64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`i32<amdgpu_synid_gfx9_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_lerp_u8 :ref:`vdst<amdgpu_synid_gfx9_vdst>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`
+ v_log_f16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_log_f32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_log_legacy_f32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_lshl_add_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`
+ v_lshl_or_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`
+ v_lshlrev_b16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`u16<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_lshlrev_b32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_lshlrev_b64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_lshrrev_b16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`u16<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_lshrrev_b32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_lshrrev_b64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`
+ v_mac_f16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mac_f32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mad_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mad_i16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`, :ref:`src2<amdgpu_synid_gfx9_src_4>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_i32_i16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`::ref:`i32<amdgpu_synid_gfx9_type_deviation>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_i32_i24 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`::ref:`i32<amdgpu_synid_gfx9_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_i64_i32 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`, :ref:`src2<amdgpu_synid_gfx9_src_9>`::ref:`i64<amdgpu_synid_gfx9_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_legacy_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_legacy_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mad_legacy_i16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`, :ref:`src2<amdgpu_synid_gfx9_src_4>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_legacy_u16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`, :ref:`src2<amdgpu_synid_gfx9_src_4>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_u16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`, :ref:`src2<amdgpu_synid_gfx9_src_4>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_u32_u16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_u32_u24 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_u64_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`, :ref:`src2<amdgpu_synid_gfx9_src_9>`::ref:`u64<amdgpu_synid_gfx9_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_max3_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_max3_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max3_i16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`, :ref:`src2<amdgpu_synid_gfx9_src_4>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_max3_i32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`
+ v_max3_u16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`, :ref:`src2<amdgpu_synid_gfx9_src_4>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_max3_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`
+ v_max_f16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_max_f32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max_f64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max_i16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_max_i32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_max_u16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_max_u32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_mbcnt_hi_u32_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_mbcnt_lo_u32_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_med3_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_med3_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_med3_i16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`, :ref:`src2<amdgpu_synid_gfx9_src_4>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_med3_i32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`
+ v_med3_u16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`, :ref:`src2<amdgpu_synid_gfx9_src_4>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_med3_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`
+ v_min3_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_min3_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_min3_i16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`, :ref:`src2<amdgpu_synid_gfx9_src_4>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_min3_i32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`
+ v_min3_u16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`, :ref:`src2<amdgpu_synid_gfx9_src_4>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_min3_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`
+ v_min_f16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_min_f32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_min_f64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_min_i16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_min_i32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_min_u16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_min_u32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_mov_b32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`
+ v_mqsad_pk_u16_u8 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`::ref:`b64<amdgpu_synid_gfx9_type_deviation>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`b64<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`, :ref:`src2<amdgpu_synid_gfx9_src_9>`::ref:`b64<amdgpu_synid_gfx9_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mqsad_u32_u8 :ref:`vdst<amdgpu_synid_gfx9_vdst_2>`::ref:`b128<amdgpu_synid_gfx9_type_deviation>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`b64<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx9_vsrc_2>`::ref:`b128<amdgpu_synid_gfx9_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_msad_u8 :ref:`vdst<amdgpu_synid_gfx9_vdst>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mul_f16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mul_f32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mul_f64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mul_hi_i32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_mul_hi_i32_i24_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_mul_hi_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_mul_hi_u32_u24_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_mul_i32_i24_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mul_legacy_f32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mul_lo_u16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`
+ v_mul_lo_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_mul_u32_u24_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>` :ref:`clamp<amdgpu_synid_clamp>`
v_nop_e64
- v_not_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`
- v_or3_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`, :ref:`src2<amdgpu_synid9_src32_5>`
- v_or_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
- v_pack_b32_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
- v_perm_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`, :ref:`src2<amdgpu_synid9_src32_5>`
- v_qsad_pk_u16_u8 :ref:`vdst<amdgpu_synid9_vdst64_0>`::ref:`b64<amdgpu_synid9_type_dev>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`b32<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_rcp_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_rcp_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rcp_f64_e64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rcp_iflag_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_readlane_b32 :ref:`sdst<amdgpu_synid9_sdst32_2>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_1>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_3>`
- v_rndne_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_rndne_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rndne_f64_e64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rsq_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_rsq_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rsq_f64_e64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sad_hi_u8 :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`u8x4<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`u8x4<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sad_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sad_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`, :ref:`src2<amdgpu_synid9_src32_5>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sad_u8 :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`u8x4<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`u8x4<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sat_pk_u8_i16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`
- v_screen_partition_4se_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`
- v_sin_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sin_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sqrt_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sqrt_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sqrt_f64_e64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sub_co_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sub_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sub_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sub_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sub_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sub_u16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sub_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>` :ref:`clamp<amdgpu_synid_clamp>`
- v_subb_co_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`, :ref:`ssrc2<amdgpu_synid9_ssrc64_1>` :ref:`clamp<amdgpu_synid_clamp>`
- v_subbrev_co_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_5>`, :ref:`src1<amdgpu_synid9_src32_5>`, :ref:`ssrc2<amdgpu_synid9_ssrc64_1>` :ref:`clamp<amdgpu_synid_clamp>`
- v_subrev_co_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_5>`, :ref:`src1<amdgpu_synid9_src32_5>` :ref:`clamp<amdgpu_synid_clamp>`
- v_subrev_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_subrev_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_subrev_u16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_7>`, :ref:`src1<amdgpu_synid9_src32_7>` :ref:`clamp<amdgpu_synid_clamp>`
- v_subrev_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_5>`, :ref:`src1<amdgpu_synid9_src32_5>` :ref:`clamp<amdgpu_synid_clamp>`
- v_trig_preop_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_trunc_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_trunc_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_trunc_f64_e64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_writelane_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_4>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_3>`
- v_xad_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`, :ref:`src2<amdgpu_synid9_src32_5>`
- v_xor_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`
+ v_not_b32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`
+ v_or3_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`
+ v_or_b32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
+ v_pack_b32_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_perm_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`
+ v_qsad_pk_u16_u8 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`::ref:`b64<amdgpu_synid_gfx9_type_deviation>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`b64<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`, :ref:`src2<amdgpu_synid_gfx9_src_9>`::ref:`b64<amdgpu_synid_gfx9_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_rcp_f16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_rcp_f32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rcp_f64_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rcp_iflag_f32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_readlane_b32 :ref:`sdst<amdgpu_synid_gfx9_sdst_7>`, :ref:`src0<amdgpu_synid_gfx9_src_5>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc_7>`
+ v_rndne_f16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_rndne_f32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rndne_f64_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rsq_f16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_rsq_f32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rsq_f64_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sad_hi_u8 :ref:`vdst<amdgpu_synid_gfx9_vdst>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`u8x4<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`u8x4<amdgpu_synid_gfx9_type_deviation>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sad_u16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`u16x2<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`u16x2<amdgpu_synid_gfx9_type_deviation>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sad_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sad_u8 :ref:`vdst<amdgpu_synid_gfx9_vdst>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`u8x4<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`u8x4<amdgpu_synid_gfx9_type_deviation>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sat_pk_u8_i16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`::ref:`u8x4<amdgpu_synid_gfx9_type_deviation>`, :ref:`src<amdgpu_synid_gfx9_src_8>`
+ v_screen_partition_4se_b32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`
+ v_sin_f16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sin_f32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sqrt_f16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sqrt_f32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sqrt_f64_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sub_co_u32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_f16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_f32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sub_i16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_i32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_u16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_u32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subb_co_u32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`, :ref:`ssrc2<amdgpu_synid_gfx9_ssrc_3>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subbrev_co_u32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`, :ref:`ssrc2<amdgpu_synid_gfx9_ssrc_3>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subrev_co_u32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subrev_f16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subrev_f32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_subrev_u16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`, :ref:`src1<amdgpu_synid_gfx9_src_4>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subrev_u32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_trig_preop_f64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src0<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_trunc_f16_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_trunc_f32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src<amdgpu_synid_gfx9_src_8>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_trunc_f64_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst_1>`, :ref:`src<amdgpu_synid_gfx9_src_9>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_writelane_b32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`ssrc0<amdgpu_synid_gfx9_ssrc_8>`, :ref:`ssrc1<amdgpu_synid_gfx9_ssrc_7>`
+ v_xad_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>`
+ v_xor_b32_e64 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`
VOP3P
-----------------------
.. parsed-literal::
- **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- v_pk_add_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_add_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_add_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_ashrrev_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_7>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_7>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
- v_pk_fma_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>`, :ref:`src2<amdgpu_synid9_src32_5>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_lshlrev_b16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_7>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_7>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
- v_pk_lshrrev_b16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_7>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_7>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
- v_pk_mad_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`, :ref:`src2<amdgpu_synid9_src32_7>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_mad_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>`, :ref:`src2<amdgpu_synid9_src32_7>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_max_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_max_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
- v_pk_max_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
- v_pk_min_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_min_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
- v_pk_min_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
- v_pk_mul_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_4>`, :ref:`src1<amdgpu_synid9_src32_5>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_mul_lo_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
- v_pk_sub_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_sub_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_6>`, :ref:`src1<amdgpu_synid9_src32_7>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_add_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_add_i16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_add_u16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_ashrrev_i16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`u16x2<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_4>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_fma_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`, :ref:`src2<amdgpu_synid_gfx9_src_1>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_lshlrev_b16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`u16x2<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_4>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_lshrrev_b16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`u16x2<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_src_4>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_mad_i16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`, :ref:`src2<amdgpu_synid_gfx9_src_4>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_mad_u16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`, :ref:`src2<amdgpu_synid_gfx9_src_4>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_max_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_max_i16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_max_u16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_min_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_min_i16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_min_u16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_mul_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_8>`, :ref:`src1<amdgpu_synid_gfx9_src_1>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_mul_lo_u16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_sub_i16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_sub_u16 :ref:`vdst<amdgpu_synid_gfx9_vdst>`, :ref:`src0<amdgpu_synid_gfx9_src_10>`, :ref:`src1<amdgpu_synid_gfx9_src_4>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
VOPC
-----------------------
.. parsed-literal::
- **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
- \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- v_cmp_class_f16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`b32<amdgpu_synid9_type_dev>`
- v_cmp_class_f16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`b32<amdgpu_synid9_type_dev>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_class_f32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`b32<amdgpu_synid9_type_dev>`
- v_cmp_class_f32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`b32<amdgpu_synid9_type_dev>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_class_f64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`b32<amdgpu_synid9_type_dev>`
- v_cmp_eq_f16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_eq_f16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_eq_f32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_eq_f32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_eq_f64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmp_eq_i16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_eq_i16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_eq_i32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_eq_i32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_eq_i64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmp_eq_u16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_eq_u16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_eq_u32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_eq_u32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_eq_u64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmp_f_f16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_f_f16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_f_f32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_f_f32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_f_f64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmp_f_i16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_f_i16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_f_i32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_f_i32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_f_i64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmp_f_u16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_f_u16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_f_u32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_f_u32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_f_u64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmp_ge_f16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_ge_f16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ge_f32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_ge_f32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ge_f64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmp_ge_i16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_ge_i16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ge_i32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_ge_i32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ge_i64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmp_ge_u16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_ge_u16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ge_u32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_ge_u32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ge_u64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmp_gt_f16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_gt_f16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_gt_f32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_gt_f32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_gt_f64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmp_gt_i16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_gt_i16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_gt_i32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_gt_i32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_gt_i64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmp_gt_u16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_gt_u16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_gt_u32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_gt_u32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_gt_u64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmp_le_f16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_le_f16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_le_f32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_le_f32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_le_f64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmp_le_i16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_le_i16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_le_i32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_le_i32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_le_i64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmp_le_u16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_le_u16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_le_u32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_le_u32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_le_u64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmp_lg_f16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_lg_f16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_lg_f32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_lg_f32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_lg_f64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmp_lt_f16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_lt_f16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_lt_f32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_lt_f32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_lt_f64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmp_lt_i16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_lt_i16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_lt_i32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_lt_i32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_lt_i64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmp_lt_u16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_lt_u16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_lt_u32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_lt_u32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_lt_u64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmp_ne_i16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_ne_i16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ne_i32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_ne_i32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ne_i64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmp_ne_u16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_ne_u16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ne_u32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_ne_u32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ne_u64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmp_neq_f16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_neq_f16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_neq_f32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_neq_f32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_neq_f64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmp_nge_f16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_nge_f16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_nge_f32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_nge_f32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_nge_f64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmp_ngt_f16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_ngt_f16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ngt_f32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_ngt_f32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ngt_f64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmp_nle_f16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_nle_f16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_nle_f32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_nle_f32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_nle_f64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmp_nlg_f16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_nlg_f16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_nlg_f32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_nlg_f32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_nlg_f64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmp_nlt_f16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_nlt_f16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_nlt_f32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_nlt_f32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_nlt_f64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmp_o_f16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_o_f16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_o_f32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_o_f32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_o_f64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmp_t_i16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_t_i16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_t_i32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_t_i32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_t_i64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmp_t_u16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_t_u16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_t_u32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_t_u32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_t_u64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmp_tru_f16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_tru_f16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_tru_f32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_tru_f32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_tru_f64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmp_u_f16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_u_f16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_u_f32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmp_u_f32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_u_f64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmpx_class_f16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`b32<amdgpu_synid9_type_dev>`
- v_cmpx_class_f16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`b32<amdgpu_synid9_type_dev>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_class_f32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`b32<amdgpu_synid9_type_dev>`
- v_cmpx_class_f32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`b32<amdgpu_synid9_type_dev>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_class_f64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`b32<amdgpu_synid9_type_dev>`
- v_cmpx_eq_f16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_eq_f16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_eq_f32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_eq_f32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_eq_f64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmpx_eq_i16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_eq_i16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_eq_i32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_eq_i32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_eq_i64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmpx_eq_u16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_eq_u16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_eq_u32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_eq_u32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_eq_u64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmpx_f_f16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_f_f16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_f_f32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_f_f32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_f_f64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmpx_f_i16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_f_i16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_f_i32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_f_i32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_f_i64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmpx_f_u16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_f_u16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_f_u32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_f_u32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_f_u64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmpx_ge_f16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_ge_f16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ge_f32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_ge_f32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ge_f64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmpx_ge_i16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_ge_i16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ge_i32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_ge_i32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ge_i64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmpx_ge_u16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_ge_u16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ge_u32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_ge_u32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ge_u64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmpx_gt_f16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_gt_f16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_gt_f32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_gt_f32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_gt_f64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmpx_gt_i16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_gt_i16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_gt_i32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_gt_i32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_gt_i64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmpx_gt_u16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_gt_u16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_gt_u32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_gt_u32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_gt_u64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmpx_le_f16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_le_f16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_le_f32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_le_f32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_le_f64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmpx_le_i16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_le_i16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_le_i32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_le_i32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_le_i64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmpx_le_u16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_le_u16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_le_u32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_le_u32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_le_u64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmpx_lg_f16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_lg_f16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_lg_f32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_lg_f32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_lg_f64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmpx_lt_f16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_lt_f16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_lt_f32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_lt_f32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_lt_f64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmpx_lt_i16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_lt_i16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_lt_i32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_lt_i32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_lt_i64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmpx_lt_u16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_lt_u16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_lt_u32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_lt_u32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_lt_u64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmpx_ne_i16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_ne_i16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ne_i32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_ne_i32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ne_i64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmpx_ne_u16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_ne_u16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ne_u32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_ne_u32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ne_u64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmpx_neq_f16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_neq_f16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_neq_f32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_neq_f32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_neq_f64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmpx_nge_f16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_nge_f16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_nge_f32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_nge_f32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_nge_f64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmpx_ngt_f16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_ngt_f16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ngt_f32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_ngt_f32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ngt_f64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmpx_nle_f16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_nle_f16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_nle_f32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_nle_f32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_nle_f64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmpx_nlg_f16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_nlg_f16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_nlg_f32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_nlg_f32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_nlg_f64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmpx_nlt_f16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_nlt_f16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_nlt_f32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_nlt_f32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_nlt_f64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmpx_o_f16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_o_f16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_o_f32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_o_f32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_o_f64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmpx_t_i16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_t_i16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_t_i32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_t_i32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_t_i64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmpx_t_u16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_t_u16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_t_u32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_t_u32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_t_u64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmpx_tru_f16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_tru_f16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_tru_f32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_tru_f32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_tru_f64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
- v_cmpx_u_f16 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_u_f16_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_u_f32 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
- v_cmpx_u_f32_sdwa :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_u_f64 :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_cmp_class_f16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`
+ v_cmp_class_f16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_class_f32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`
+ v_cmp_class_f32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_class_f64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`
+ v_cmp_eq_f16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_eq_f16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_f32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_eq_f32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_f64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmp_eq_i16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_eq_i16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_i32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_eq_i32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_i64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmp_eq_u16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_eq_u16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_u32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_eq_u32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_u64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmp_f_f16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_f_f16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_f_f32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_f_f32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_f_f64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmp_f_i16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_f_i16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_f_i32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_f_i32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_f_i64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmp_f_u16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_f_u16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_f_u32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_f_u32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_f_u64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmp_ge_f16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_ge_f16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_f32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_ge_f32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_f64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmp_ge_i16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_ge_i16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_i32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_ge_i32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_i64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmp_ge_u16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_ge_u16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_u32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_ge_u32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_u64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmp_gt_f16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_gt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_f32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_gt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_f64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmp_gt_i16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_gt_i16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_i32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_gt_i32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_i64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmp_gt_u16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_gt_u16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_u32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_gt_u32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_u64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmp_le_f16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_le_f16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_f32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_le_f32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_f64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmp_le_i16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_le_i16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_i32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_le_i32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_i64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmp_le_u16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_le_u16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_u32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_le_u32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_u64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmp_lg_f16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_lg_f16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lg_f32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_lg_f32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lg_f64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmp_lt_f16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_lt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_f32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_lt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_f64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmp_lt_i16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_lt_i16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_i32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_lt_i32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_i64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmp_lt_u16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_lt_u16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_u32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_lt_u32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_u64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmp_ne_i16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_ne_i16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ne_i32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_ne_i32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ne_i64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmp_ne_u16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_ne_u16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ne_u32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_ne_u32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ne_u64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmp_neq_f16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_neq_f16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_neq_f32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_neq_f32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_neq_f64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmp_nge_f16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_nge_f16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nge_f32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_nge_f32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nge_f64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmp_ngt_f16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_ngt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ngt_f32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_ngt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ngt_f64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmp_nle_f16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_nle_f16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nle_f32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_nle_f32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nle_f64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmp_nlg_f16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_nlg_f16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nlg_f32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_nlg_f32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nlg_f64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmp_nlt_f16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_nlt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nlt_f32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_nlt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nlt_f64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmp_o_f16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_o_f16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_o_f32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_o_f32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_o_f64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmp_t_i16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_t_i16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_t_i32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_t_i32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_t_i64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmp_t_u16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_t_u16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_t_u32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_t_u32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_t_u64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmp_tru_f16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_tru_f16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_tru_f32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_tru_f32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_tru_f64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmp_u_f16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_u_f16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_u_f32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmp_u_f32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_2>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_u_f64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmpx_class_f16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`
+ v_cmpx_class_f16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_class_f32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`
+ v_cmpx_class_f32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_class_f64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`::ref:`b32<amdgpu_synid_gfx9_type_deviation>`
+ v_cmpx_eq_f16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_eq_f16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_f32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_eq_f32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_f64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmpx_eq_i16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_eq_i16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_i32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_eq_i32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_i64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmpx_eq_u16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_eq_u16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_u32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_eq_u32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_u64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmpx_f_f16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_f_f16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_f_f32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_f_f32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_f_f64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmpx_f_i16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_f_i16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_f_i32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_f_i32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_f_i64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmpx_f_u16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_f_u16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_f_u32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_f_u32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_f_u64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmpx_ge_f16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_ge_f16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_f32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_ge_f32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_f64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmpx_ge_i16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_ge_i16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_i32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_ge_i32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_i64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmpx_ge_u16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_ge_u16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_u32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_ge_u32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_u64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmpx_gt_f16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_gt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_f32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_gt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_f64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmpx_gt_i16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_gt_i16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_i32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_gt_i32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_i64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmpx_gt_u16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_gt_u16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_u32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_gt_u32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_u64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmpx_le_f16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_le_f16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_f32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_le_f32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_f64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmpx_le_i16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_le_i16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_i32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_le_i32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_i64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmpx_le_u16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_le_u16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_u32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_le_u32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_u64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmpx_lg_f16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_lg_f16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lg_f32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_lg_f32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lg_f64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmpx_lt_f16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_lt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_f32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_lt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_f64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmpx_lt_i16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_lt_i16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_i32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_lt_i32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_i64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmpx_lt_u16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_lt_u16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_u32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_lt_u32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_u64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmpx_ne_i16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_ne_i16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ne_i32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_ne_i32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ne_i64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmpx_ne_u16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_ne_u16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ne_u32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_ne_u32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ne_u64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmpx_neq_f16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_neq_f16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_neq_f32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_neq_f32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_neq_f64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmpx_nge_f16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_nge_f16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nge_f32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_nge_f32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nge_f64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmpx_ngt_f16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_ngt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ngt_f32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_ngt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ngt_f64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmpx_nle_f16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_nle_f16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nle_f32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_nle_f32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nle_f64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmpx_nlg_f16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_nlg_f16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nlg_f32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_nlg_f32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nlg_f64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmpx_nlt_f16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_nlt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nlt_f32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_nlt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nlt_f64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmpx_o_f16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_o_f16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_o_f32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_o_f32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_o_f64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmpx_t_i16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_t_i16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_t_i32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_t_i32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_t_i64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmpx_t_u16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_t_u16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_4>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_t_u32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_t_u32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_t_u64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmpx_tru_f16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_tru_f16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_tru_f32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_tru_f32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_tru_f64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
+ v_cmpx_u_f16 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_u_f16_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_u_f32 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_1>`
+ v_cmpx_u_f32_sdwa :ref:`sdst<amdgpu_synid_gfx9_sdst_6>`, :ref:`src0<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>`, :ref:`src1<amdgpu_synid_gfx9_src_1>`::ref:`m<amdgpu_synid_gfx9_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_u_f64 :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx9_vsrc_3>`
.. |---| unicode:: U+02014 .. em dash
-
.. toctree::
:hidden:
gfx9_attr
- gfx9_bimm16
- gfx9_bimm32
- gfx9_fimm16
- gfx9_fimm32
+ gfx9_dst
gfx9_hwreg
gfx9_imask
+ gfx9_imm16
+ gfx9_imm16_1
+ gfx9_imm16_2
gfx9_label
+ gfx9_m
+ gfx9_m_1
gfx9_msg
+ gfx9_opt
gfx9_param
- gfx9_perm_smem
- gfx9_simm16
+ gfx9_probe
+ gfx9_saddr
+ gfx9_saddr_1
+ gfx9_sbase
+ gfx9_sbase_1
+ gfx9_sbase_2
+ gfx9_sdata
+ gfx9_sdata_1
+ gfx9_sdata_2
+ gfx9_sdata_3
+ gfx9_sdata_4
+ gfx9_sdata_5
+ gfx9_sdst
+ gfx9_sdst_1
+ gfx9_sdst_2
+ gfx9_sdst_3
+ gfx9_sdst_4
+ gfx9_sdst_5
+ gfx9_sdst_6
+ gfx9_sdst_7
+ gfx9_simm32
+ gfx9_simm32_1
+ gfx9_simm32_2
+ gfx9_soffset
+ gfx9_soffset_1
+ gfx9_soffset_2
+ gfx9_src
+ gfx9_src_1
+ gfx9_src_10
+ gfx9_src_2
+ gfx9_src_3
+ gfx9_src_4
+ gfx9_src_5
+ gfx9_src_6
+ gfx9_src_7
+ gfx9_src_8
+ gfx9_src_9
+ gfx9_srsrc
+ gfx9_srsrc_1
+ gfx9_ssamp
+ gfx9_ssrc
+ gfx9_ssrc_1
+ gfx9_ssrc_2
+ gfx9_ssrc_3
+ gfx9_ssrc_4
+ gfx9_ssrc_5
+ gfx9_ssrc_6
+ gfx9_ssrc_7
+ gfx9_ssrc_8
gfx9_tgt
- gfx9_uimm16
+ gfx9_type_deviation
+ gfx9_vaddr
+ gfx9_vaddr_1
+ gfx9_vaddr_2
+ gfx9_vaddr_3
+ gfx9_vaddr_4
+ gfx9_vaddr_5
+ gfx9_vcc
+ gfx9_vdata
+ gfx9_vdata0
+ gfx9_vdata0_1
+ gfx9_vdata1
+ gfx9_vdata1_1
+ gfx9_vdata_1
+ gfx9_vdata_10
+ gfx9_vdata_2
+ gfx9_vdata_3
+ gfx9_vdata_4
+ gfx9_vdata_5
+ gfx9_vdata_6
+ gfx9_vdata_7
+ gfx9_vdata_8
+ gfx9_vdata_9
+ gfx9_vdst
+ gfx9_vdst_1
+ gfx9_vdst_10
+ gfx9_vdst_11
+ gfx9_vdst_12
+ gfx9_vdst_13
+ gfx9_vdst_2
+ gfx9_vdst_3
+ gfx9_vdst_4
+ gfx9_vdst_5
+ gfx9_vdst_6
+ gfx9_vdst_7
+ gfx9_vdst_8
+ gfx9_vdst_9
+ gfx9_vsrc
+ gfx9_vsrc_1
+ gfx9_vsrc_2
+ gfx9_vsrc_3
gfx9_waitcnt
- gfx9_addr_buf
- gfx9_addr_ds
- gfx9_addr_flat
- gfx9_addr_mimg
- gfx9_base_smem_addr
- gfx9_base_smem_buf
- gfx9_base_smem_scratch
- gfx9_data_buf_atomic128
- gfx9_data_buf_atomic32
- gfx9_data_buf_atomic64
- gfx9_data_mimg_atomic_cmp
- gfx9_data_mimg_atomic_reg
- gfx9_data_mimg_store
- gfx9_data_mimg_store_d16
- gfx9_data_smem_atomic128
- gfx9_data_smem_atomic32
- gfx9_data_smem_atomic64
- gfx9_dst_buf_128
- gfx9_dst_buf_32
- gfx9_dst_buf_64
- gfx9_dst_buf_96
- gfx9_dst_buf_lds
- gfx9_dst_flat_atomic32
- gfx9_dst_flat_atomic64
- gfx9_dst_mimg_gather4
- gfx9_dst_mimg_regular
- gfx9_dst_mimg_regular_d16
- gfx9_offset_buf
- gfx9_offset_smem_buf
- gfx9_offset_smem_plain
- gfx9_rsrc_buf
- gfx9_rsrc_mimg
- gfx9_saddr_flat_global
- gfx9_saddr_flat_scratch
- gfx9_samp_mimg
- gfx9_sdata128_0
- gfx9_sdata32_0
- gfx9_sdata64_0
- gfx9_sdst128_0
- gfx9_sdst256_0
- gfx9_sdst32_0
- gfx9_sdst32_1
- gfx9_sdst32_2
- gfx9_sdst512_0
- gfx9_sdst64_0
- gfx9_sdst64_1
- gfx9_src32_0
- gfx9_src32_1
- gfx9_src32_2
- gfx9_src32_3
- gfx9_src32_4
- gfx9_src32_5
- gfx9_src32_6
- gfx9_src32_7
- gfx9_src64_0
- gfx9_src64_1
- gfx9_src_exp
- gfx9_ssrc32_0
- gfx9_ssrc32_1
- gfx9_ssrc32_2
- gfx9_ssrc32_3
- gfx9_ssrc32_4
- gfx9_ssrc64_0
- gfx9_ssrc64_1
- gfx9_ssrc64_2
- gfx9_ssrc64_3
- gfx9_vaddr_flat_global
- gfx9_vaddr_flat_scratch
- gfx9_vcc_64
- gfx9_vdata128_0
- gfx9_vdata32_0
- gfx9_vdata64_0
- gfx9_vdata96_0
- gfx9_vdst128_0
- gfx9_vdst32_0
- gfx9_vdst64_0
- gfx9_vdst96_0
- gfx9_vsrc128_0
- gfx9_vsrc32_0
- gfx9_vsrc32_1
- gfx9_vsrc64_0
- gfx9_mod_dpp_sdwa_abs_neg
- gfx9_mod_sdwa_sext
- gfx9_mod_vop3_abs_neg
- gfx9_opt
- gfx9_ret
- gfx9_type_dev
diff --git a/llvm/docs/AMDGPU/gfx9_attr.rst b/llvm/docs/AMDGPU/gfx9_attr.rst
index 10d1b120bc09..cf927e63fefc 100644
--- a/llvm/docs/AMDGPU/gfx9_attr.rst
+++ b/llvm/docs/AMDGPU/gfx9_attr.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_attr:
+.. _amdgpu_synid_gfx9_attr:
attr
-===========================
+====
Interpolation attribute and channel:
diff --git a/llvm/docs/AMDGPU/gfx9_ret.rst b/llvm/docs/AMDGPU/gfx9_dst.rst
similarity index 88%
rename from llvm/docs/AMDGPU/gfx9_ret.rst
rename to llvm/docs/AMDGPU/gfx9_dst.rst
index 6f132293bcb3..2d72a6cbd391 100644
--- a/llvm/docs/AMDGPU/gfx9_ret.rst
+++ b/llvm/docs/AMDGPU/gfx9_dst.rst
@@ -5,9 +5,9 @@
* *
**************************************************
-.. _amdgpu_synid9_ret:
+.. _amdgpu_synid_gfx9_dst:
dst
-===========================
+===
This is an input operand. It may optionally serve as a destination if :ref:`glc<amdgpu_synid_glc>` is specified.
diff --git a/llvm/docs/AMDGPU/gfx9_hwreg.rst b/llvm/docs/AMDGPU/gfx9_hwreg.rst
index 04473ec84c76..94add314cd07 100644
--- a/llvm/docs/AMDGPU/gfx9_hwreg.rst
+++ b/llvm/docs/AMDGPU/gfx9_hwreg.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_hwreg:
+.. _amdgpu_synid_gfx9_hwreg:
hwreg
-===========================
+=====
Bits of a hardware register being accessed.
diff --git a/llvm/docs/AMDGPU/gfx9_imask.rst b/llvm/docs/AMDGPU/gfx9_imask.rst
index c0cc3723069d..393918167754 100644
--- a/llvm/docs/AMDGPU/gfx9_imask.rst
+++ b/llvm/docs/AMDGPU/gfx9_imask.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_imask:
+.. _amdgpu_synid_gfx9_imask:
imask
-===========================
+=====
This operand is a mask which controls indexing mode for operands of subsequent instructions.
Bits 0, 1 and 2 control indexing of *src0*, *src1* and *src2*, while bit 3 controls indexing of *dst*.
diff --git a/llvm/docs/AMDGPU/gfx9_simm16.rst b/llvm/docs/AMDGPU/gfx9_imm16.rst
similarity index 89%
rename from llvm/docs/AMDGPU/gfx9_simm16.rst
rename to llvm/docs/AMDGPU/gfx9_imm16.rst
index 6bc9ba70da0b..713a63b1af53 100644
--- a/llvm/docs/AMDGPU/gfx9_simm16.rst
+++ b/llvm/docs/AMDGPU/gfx9_imm16.rst
@@ -5,9 +5,9 @@
* *
**************************************************
-.. _amdgpu_synid9_simm16:
+.. _amdgpu_synid_gfx9_imm16:
imm16
-===========================
+=====
An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
diff --git a/llvm/docs/AMDGPU/gfx9_uimm16.rst b/llvm/docs/AMDGPU/gfx9_imm16_1.rst
similarity index 89%
rename from llvm/docs/AMDGPU/gfx9_uimm16.rst
rename to llvm/docs/AMDGPU/gfx9_imm16_1.rst
index c14915b01211..2ce77ef48d60 100644
--- a/llvm/docs/AMDGPU/gfx9_uimm16.rst
+++ b/llvm/docs/AMDGPU/gfx9_imm16_1.rst
@@ -5,9 +5,9 @@
* *
**************************************************
-.. _amdgpu_synid9_uimm16:
+.. _amdgpu_synid_gfx9_imm16_1:
imm16
-===========================
+=====
An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..65535.
diff --git a/llvm/docs/AMDGPU/gfx9_bimm16.rst b/llvm/docs/AMDGPU/gfx9_imm16_2.rst
similarity index 89%
rename from llvm/docs/AMDGPU/gfx9_bimm16.rst
rename to llvm/docs/AMDGPU/gfx9_imm16_2.rst
index 47930426f4fe..f71887425af5 100644
--- a/llvm/docs/AMDGPU/gfx9_bimm16.rst
+++ b/llvm/docs/AMDGPU/gfx9_imm16_2.rst
@@ -5,9 +5,9 @@
* *
**************************************************
-.. _amdgpu_synid9_bimm16:
+.. _amdgpu_synid_gfx9_imm16_2:
imm16
-===========================
+=====
A 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
diff --git a/llvm/docs/AMDGPU/gfx9_label.rst b/llvm/docs/AMDGPU/gfx9_label.rst
index 1f4c8465bab7..b114979e5f66 100644
--- a/llvm/docs/AMDGPU/gfx9_label.rst
+++ b/llvm/docs/AMDGPU/gfx9_label.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_label:
+.. _amdgpu_synid_gfx9_label:
label
-===========================
+=====
A branch target which is a 16-bit signed integer treated as a PC-relative dword offset.
diff --git a/llvm/docs/AMDGPU/gfx9_mod_sdwa_sext.rst b/llvm/docs/AMDGPU/gfx9_m.rst
similarity index 85%
rename from llvm/docs/AMDGPU/gfx9_mod_sdwa_sext.rst
rename to llvm/docs/AMDGPU/gfx9_m.rst
index f0adfa6d4acf..e7759aa13529 100644
--- a/llvm/docs/AMDGPU/gfx9_mod_sdwa_sext.rst
+++ b/llvm/docs/AMDGPU/gfx9_m.rst
@@ -5,9 +5,9 @@
* *
**************************************************
-.. _amdgpu_synid9_mod_sdwa_sext:
+.. _amdgpu_synid_gfx9_m:
m
-===========================
+=
This operand may be used with integer operand modifier :ref:`sext<amdgpu_synid_sext>`.
diff --git a/llvm/docs/AMDGPU/gfx9_mod_vop3_abs_neg.rst b/llvm/docs/AMDGPU/gfx9_m_1.rst
similarity index 86%
rename from llvm/docs/AMDGPU/gfx9_mod_vop3_abs_neg.rst
rename to llvm/docs/AMDGPU/gfx9_m_1.rst
index c7f33436b351..f4dec5955e7b 100644
--- a/llvm/docs/AMDGPU/gfx9_mod_vop3_abs_neg.rst
+++ b/llvm/docs/AMDGPU/gfx9_m_1.rst
@@ -5,9 +5,9 @@
* *
**************************************************
-.. _amdgpu_synid9_mod_vop3_abs_neg:
+.. _amdgpu_synid_gfx9_m_1:
m
-===========================
+=
This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
diff --git a/llvm/docs/AMDGPU/gfx9_mod_dpp_sdwa_abs_neg.rst b/llvm/docs/AMDGPU/gfx9_mod_dpp_sdwa_abs_neg.rst
deleted file mode 100644
index b3e9fc2730b9..000000000000
--- a/llvm/docs/AMDGPU/gfx9_mod_dpp_sdwa_abs_neg.rst
+++ /dev/null
@@ -1,13 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid9_mod_dpp_sdwa_abs_neg:
-
-m
-===========================
-
-This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
diff --git a/llvm/docs/AMDGPU/gfx9_msg.rst b/llvm/docs/AMDGPU/gfx9_msg.rst
index 34ede7100381..efb95e5a97db 100644
--- a/llvm/docs/AMDGPU/gfx9_msg.rst
+++ b/llvm/docs/AMDGPU/gfx9_msg.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_msg:
+.. _amdgpu_synid_gfx9_msg:
msg
-===========================
+===
A 16-bit message code. The bits of this operand have the following meaning:
@@ -94,4 +94,3 @@ Examples:
stream = 1
s_sendmsg sendmsg(msg, op, stream)
s_sendmsg sendmsg(2, GS_OP_CUT)
-
diff --git a/llvm/docs/AMDGPU/gfx9_opt.rst b/llvm/docs/AMDGPU/gfx9_opt.rst
index 19eefec0b4ec..913bb51b0399 100644
--- a/llvm/docs/AMDGPU/gfx9_opt.rst
+++ b/llvm/docs/AMDGPU/gfx9_opt.rst
@@ -5,9 +5,9 @@
* *
**************************************************
-.. _amdgpu_synid9_opt:
+.. _amdgpu_synid_gfx9_opt:
opt
-===========================
+===
This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
diff --git a/llvm/docs/AMDGPU/gfx9_param.rst b/llvm/docs/AMDGPU/gfx9_param.rst
index 234fbc512ed0..3afbd1ce880f 100644
--- a/llvm/docs/AMDGPU/gfx9_param.rst
+++ b/llvm/docs/AMDGPU/gfx9_param.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_param:
+.. _amdgpu_synid_gfx9_param:
param
-===========================
+=====
Interpolation parameter to read:
diff --git a/llvm/docs/AMDGPU/gfx9_perm_smem.rst b/llvm/docs/AMDGPU/gfx9_probe.rst
similarity index 93%
rename from llvm/docs/AMDGPU/gfx9_perm_smem.rst
rename to llvm/docs/AMDGPU/gfx9_probe.rst
index 0d24d5f16e46..f943fed8f4c4 100644
--- a/llvm/docs/AMDGPU/gfx9_perm_smem.rst
+++ b/llvm/docs/AMDGPU/gfx9_probe.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_perm_smem:
+.. _amdgpu_synid_gfx9_probe:
-imm3
-===========================
+probe
+=====
A bit mask which indicates request permissions.
diff --git a/llvm/docs/AMDGPU/gfx9_saddr_flat_global.rst b/llvm/docs/AMDGPU/gfx9_saddr.rst
similarity index 58%
rename from llvm/docs/AMDGPU/gfx9_saddr_flat_global.rst
rename to llvm/docs/AMDGPU/gfx9_saddr.rst
index 7396df0bc726..442f523d7343 100644
--- a/llvm/docs/AMDGPU/gfx9_saddr_flat_global.rst
+++ b/llvm/docs/AMDGPU/gfx9_saddr.rst
@@ -5,15 +5,15 @@
* *
**************************************************
-.. _amdgpu_synid9_saddr_flat_global:
+.. _amdgpu_synid_gfx9_saddr:
saddr
-===========================
+=====
An optional 64-bit flat global address. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
-See :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>` for description of available addressing modes.
+See :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>` for description of available addressing modes.
*Size:* 2 dwords.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`off<amdgpu_synid_off>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`off<amdgpu_synid_off>`
diff --git a/llvm/docs/AMDGPU/gfx9_saddr_flat_scratch.rst b/llvm/docs/AMDGPU/gfx9_saddr_1.rst
similarity index 56%
rename from llvm/docs/AMDGPU/gfx9_saddr_flat_scratch.rst
rename to llvm/docs/AMDGPU/gfx9_saddr_1.rst
index 5bdbf394af1a..b2a9277514a8 100644
--- a/llvm/docs/AMDGPU/gfx9_saddr_flat_scratch.rst
+++ b/llvm/docs/AMDGPU/gfx9_saddr_1.rst
@@ -5,15 +5,15 @@
* *
**************************************************
-.. _amdgpu_synid9_saddr_flat_scratch:
+.. _amdgpu_synid_gfx9_saddr_1:
saddr
-===========================
+=====
An optional 32-bit flat scratch offset. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
-Either this operand or :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>` must be set to :ref:`off<amdgpu_synid_off>`.
+Either this operand or :ref:`vaddr<amdgpu_synid_gfx9_vaddr_3>` must be set to :ref:`off<amdgpu_synid_off>`.
*Size:* 1 dword.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`off<amdgpu_synid_off>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`off<amdgpu_synid_off>`
diff --git a/llvm/docs/AMDGPU/gfx9_base_smem_addr.rst b/llvm/docs/AMDGPU/gfx9_sbase.rst
similarity index 70%
rename from llvm/docs/AMDGPU/gfx9_base_smem_addr.rst
rename to llvm/docs/AMDGPU/gfx9_sbase.rst
index 63c2cbd5fbd2..9ab35cfdb853 100644
--- a/llvm/docs/AMDGPU/gfx9_base_smem_addr.rst
+++ b/llvm/docs/AMDGPU/gfx9_sbase.rst
@@ -5,13 +5,13 @@
* *
**************************************************
-.. _amdgpu_synid9_base_smem_addr:
+.. _amdgpu_synid_gfx9_sbase:
sbase
-===========================
+=====
A 64-bit base address for scalar memory operations.
*Size:* 2 dwords.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx9_base_smem_buf.rst b/llvm/docs/AMDGPU/gfx9_sbase_1.rst
similarity index 88%
rename from llvm/docs/AMDGPU/gfx9_base_smem_buf.rst
rename to llvm/docs/AMDGPU/gfx9_sbase_1.rst
index 191ecbaeabe4..7ddb7347f364 100644
--- a/llvm/docs/AMDGPU/gfx9_base_smem_buf.rst
+++ b/llvm/docs/AMDGPU/gfx9_sbase_1.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_base_smem_buf:
+.. _amdgpu_synid_gfx9_sbase_1:
sbase
-===========================
+=====
A 128-bit buffer resource constant for scalar memory operations which provides a base address, a size and a stride.
diff --git a/llvm/docs/AMDGPU/gfx9_base_smem_scratch.rst b/llvm/docs/AMDGPU/gfx9_sbase_2.rst
similarity index 72%
rename from llvm/docs/AMDGPU/gfx9_base_smem_scratch.rst
rename to llvm/docs/AMDGPU/gfx9_sbase_2.rst
index 83fd760d75af..69a9c77e63a5 100644
--- a/llvm/docs/AMDGPU/gfx9_base_smem_scratch.rst
+++ b/llvm/docs/AMDGPU/gfx9_sbase_2.rst
@@ -5,13 +5,13 @@
* *
**************************************************
-.. _amdgpu_synid9_base_smem_scratch:
+.. _amdgpu_synid_gfx9_sbase_2:
sbase
-===========================
+=====
This operand is ignored by H/W and :ref:`flat_scratch<amdgpu_synid_flat_scratch>` is supplied instead.
*Size:* 2 dwords.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx9_data_smem_atomic32.rst b/llvm/docs/AMDGPU/gfx9_sdata.rst
similarity index 74%
rename from llvm/docs/AMDGPU/gfx9_data_smem_atomic32.rst
rename to llvm/docs/AMDGPU/gfx9_sdata.rst
index 9ad25f3403de..b76aea265e8a 100644
--- a/llvm/docs/AMDGPU/gfx9_data_smem_atomic32.rst
+++ b/llvm/docs/AMDGPU/gfx9_sdata.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_data_smem_atomic32:
+.. _amdgpu_synid_gfx9_sdata:
sdata
-===========================
+=====
Input data for an atomic instruction.
@@ -18,4 +18,4 @@ Optionally may serve as an output data:
*Size:* 1 dword.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx9_data_smem_atomic64.rst b/llvm/docs/AMDGPU/gfx9_sdata_1.rst
similarity index 74%
rename from llvm/docs/AMDGPU/gfx9_data_smem_atomic64.rst
rename to llvm/docs/AMDGPU/gfx9_sdata_1.rst
index 6f67bffbd548..eff06aecf6de 100644
--- a/llvm/docs/AMDGPU/gfx9_data_smem_atomic64.rst
+++ b/llvm/docs/AMDGPU/gfx9_sdata_1.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_data_smem_atomic64:
+.. _amdgpu_synid_gfx9_sdata_1:
sdata
-===========================
+=====
Input data for an atomic instruction.
@@ -18,4 +18,4 @@ Optionally may serve as an output data:
*Size:* 2 dwords.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx9_data_smem_atomic128.rst b/llvm/docs/AMDGPU/gfx9_sdata_2.rst
similarity index 89%
rename from llvm/docs/AMDGPU/gfx9_data_smem_atomic128.rst
rename to llvm/docs/AMDGPU/gfx9_sdata_2.rst
index 677361894818..af0f92ee207c 100644
--- a/llvm/docs/AMDGPU/gfx9_data_smem_atomic128.rst
+++ b/llvm/docs/AMDGPU/gfx9_sdata_2.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_data_smem_atomic128:
+.. _amdgpu_synid_gfx9_sdata_2:
sdata
-===========================
+=====
Input data for an atomic instruction.
diff --git a/llvm/docs/AMDGPU/gfx9_sdata32_0.rst b/llvm/docs/AMDGPU/gfx9_sdata_3.rst
similarity index 69%
rename from llvm/docs/AMDGPU/gfx9_sdata32_0.rst
rename to llvm/docs/AMDGPU/gfx9_sdata_3.rst
index 4de36350dc7a..7f4bd43ac1ab 100644
--- a/llvm/docs/AMDGPU/gfx9_sdata32_0.rst
+++ b/llvm/docs/AMDGPU/gfx9_sdata_3.rst
@@ -5,13 +5,13 @@
* *
**************************************************
-.. _amdgpu_synid9_sdata32_0:
+.. _amdgpu_synid_gfx9_sdata_3:
sdata
-===========================
+=====
Instruction input.
*Size:* 1 dword.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx9_sdata64_0.rst b/llvm/docs/AMDGPU/gfx9_sdata_4.rst
similarity index 69%
rename from llvm/docs/AMDGPU/gfx9_sdata64_0.rst
rename to llvm/docs/AMDGPU/gfx9_sdata_4.rst
index 7cde210d7b4f..e63b71b71e53 100644
--- a/llvm/docs/AMDGPU/gfx9_sdata64_0.rst
+++ b/llvm/docs/AMDGPU/gfx9_sdata_4.rst
@@ -5,13 +5,13 @@
* *
**************************************************
-.. _amdgpu_synid9_sdata64_0:
+.. _amdgpu_synid_gfx9_sdata_4:
sdata
-===========================
+=====
Instruction input.
*Size:* 2 dwords.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx9_sdata128_0.rst b/llvm/docs/AMDGPU/gfx9_sdata_5.rst
similarity index 87%
rename from llvm/docs/AMDGPU/gfx9_sdata128_0.rst
rename to llvm/docs/AMDGPU/gfx9_sdata_5.rst
index d3609d497f66..57b13d24e285 100644
--- a/llvm/docs/AMDGPU/gfx9_sdata128_0.rst
+++ b/llvm/docs/AMDGPU/gfx9_sdata_5.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_sdata128_0:
+.. _amdgpu_synid_gfx9_sdata_5:
sdata
-===========================
+=====
Instruction input.
diff --git a/llvm/docs/AMDGPU/gfx9_sdst32_0.rst b/llvm/docs/AMDGPU/gfx9_sdst.rst
similarity index 69%
rename from llvm/docs/AMDGPU/gfx9_sdst32_0.rst
rename to llvm/docs/AMDGPU/gfx9_sdst.rst
index 911c843e7f47..c6d93c746fed 100644
--- a/llvm/docs/AMDGPU/gfx9_sdst32_0.rst
+++ b/llvm/docs/AMDGPU/gfx9_sdst.rst
@@ -5,13 +5,13 @@
* *
**************************************************
-.. _amdgpu_synid9_sdst32_0:
+.. _amdgpu_synid_gfx9_sdst:
sdst
-===========================
+====
Instruction output.
*Size:* 1 dword.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx9_sdst512_0.rst b/llvm/docs/AMDGPU/gfx9_sdst_1.rst
similarity index 87%
rename from llvm/docs/AMDGPU/gfx9_sdst512_0.rst
rename to llvm/docs/AMDGPU/gfx9_sdst_1.rst
index 7f7dab60aa42..3687964c95af 100644
--- a/llvm/docs/AMDGPU/gfx9_sdst512_0.rst
+++ b/llvm/docs/AMDGPU/gfx9_sdst_1.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_sdst512_0:
+.. _amdgpu_synid_gfx9_sdst_1:
sdst
-===========================
+====
Instruction output.
diff --git a/llvm/docs/AMDGPU/gfx9_sdst64_0.rst b/llvm/docs/AMDGPU/gfx9_sdst_2.rst
similarity index 69%
rename from llvm/docs/AMDGPU/gfx9_sdst64_0.rst
rename to llvm/docs/AMDGPU/gfx9_sdst_2.rst
index dc5f4c72fb98..3f2e0270d22e 100644
--- a/llvm/docs/AMDGPU/gfx9_sdst64_0.rst
+++ b/llvm/docs/AMDGPU/gfx9_sdst_2.rst
@@ -5,13 +5,13 @@
* *
**************************************************
-.. _amdgpu_synid9_sdst64_0:
+.. _amdgpu_synid_gfx9_sdst_2:
sdst
-===========================
+====
Instruction output.
*Size:* 2 dwords.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx9_sdst128_0.rst b/llvm/docs/AMDGPU/gfx9_sdst_3.rst
similarity index 87%
rename from llvm/docs/AMDGPU/gfx9_sdst128_0.rst
rename to llvm/docs/AMDGPU/gfx9_sdst_3.rst
index 974df548f465..fc53889b86f7 100644
--- a/llvm/docs/AMDGPU/gfx9_sdst128_0.rst
+++ b/llvm/docs/AMDGPU/gfx9_sdst_3.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_sdst128_0:
+.. _amdgpu_synid_gfx9_sdst_3:
sdst
-===========================
+====
Instruction output.
diff --git a/llvm/docs/AMDGPU/gfx9_sdst256_0.rst b/llvm/docs/AMDGPU/gfx9_sdst_4.rst
similarity index 87%
rename from llvm/docs/AMDGPU/gfx9_sdst256_0.rst
rename to llvm/docs/AMDGPU/gfx9_sdst_4.rst
index b492921d47a5..9f5c4eee3792 100644
--- a/llvm/docs/AMDGPU/gfx9_sdst256_0.rst
+++ b/llvm/docs/AMDGPU/gfx9_sdst_4.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_sdst256_0:
+.. _amdgpu_synid_gfx9_sdst_4:
sdst
-===========================
+====
Instruction output.
diff --git a/llvm/docs/AMDGPU/gfx9_sdst32_1.rst b/llvm/docs/AMDGPU/gfx9_sdst_5.rst
similarity index 62%
rename from llvm/docs/AMDGPU/gfx9_sdst32_1.rst
rename to llvm/docs/AMDGPU/gfx9_sdst_5.rst
index 8f63024f1872..7987c7fb053c 100644
--- a/llvm/docs/AMDGPU/gfx9_sdst32_1.rst
+++ b/llvm/docs/AMDGPU/gfx9_sdst_5.rst
@@ -5,13 +5,13 @@
* *
**************************************************
-.. _amdgpu_synid9_sdst32_1:
+.. _amdgpu_synid_gfx9_sdst_5:
sdst
-===========================
+====
Instruction output.
*Size:* 1 dword.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`
diff --git a/llvm/docs/AMDGPU/gfx9_sdst64_1.rst b/llvm/docs/AMDGPU/gfx9_sdst_6.rst
similarity index 65%
rename from llvm/docs/AMDGPU/gfx9_sdst64_1.rst
rename to llvm/docs/AMDGPU/gfx9_sdst_6.rst
index 208d68b41715..80bbd65fb6f5 100644
--- a/llvm/docs/AMDGPU/gfx9_sdst64_1.rst
+++ b/llvm/docs/AMDGPU/gfx9_sdst_6.rst
@@ -5,13 +5,13 @@
* *
**************************************************
-.. _amdgpu_synid9_sdst64_1:
+.. _amdgpu_synid_gfx9_sdst_6:
sdst
-===========================
+====
Instruction output.
*Size:* 2 dwords.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`
diff --git a/llvm/docs/AMDGPU/gfx9_sdst32_2.rst b/llvm/docs/AMDGPU/gfx9_sdst_7.rst
similarity index 73%
rename from llvm/docs/AMDGPU/gfx9_sdst32_2.rst
rename to llvm/docs/AMDGPU/gfx9_sdst_7.rst
index 04f3cda2d08a..425a331e20b7 100644
--- a/llvm/docs/AMDGPU/gfx9_sdst32_2.rst
+++ b/llvm/docs/AMDGPU/gfx9_sdst_7.rst
@@ -5,13 +5,13 @@
* *
**************************************************
-.. _amdgpu_synid9_sdst32_2:
+.. _amdgpu_synid_gfx9_sdst_7:
sdst
-===========================
+====
Instruction output.
*Size:* 1 dword.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx9_bimm32.rst b/llvm/docs/AMDGPU/gfx9_simm32.rst
similarity index 87%
rename from llvm/docs/AMDGPU/gfx9_bimm32.rst
rename to llvm/docs/AMDGPU/gfx9_simm32.rst
index 4ac0a97e9521..7e8521351c8a 100644
--- a/llvm/docs/AMDGPU/gfx9_bimm32.rst
+++ b/llvm/docs/AMDGPU/gfx9_simm32.rst
@@ -5,9 +5,9 @@
* *
**************************************************
-.. _amdgpu_synid9_bimm32:
+.. _amdgpu_synid_gfx9_simm32:
-imm32
-===========================
+simm32
+======
An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value is truncated to 32 bits.
diff --git a/llvm/docs/AMDGPU/gfx9_fimm16.rst b/llvm/docs/AMDGPU/gfx9_simm32_1.rst
similarity index 90%
rename from llvm/docs/AMDGPU/gfx9_fimm16.rst
rename to llvm/docs/AMDGPU/gfx9_simm32_1.rst
index 75d3b758a680..00d0de18847f 100644
--- a/llvm/docs/AMDGPU/gfx9_fimm16.rst
+++ b/llvm/docs/AMDGPU/gfx9_simm32_1.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_fimm16:
+.. _amdgpu_synid_gfx9_simm32_1:
-imm32
-===========================
+simm32
+======
A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
The value is converted to *f16* as described :ref:`here<amdgpu_synid_fp_conv>`.
diff --git a/llvm/docs/AMDGPU/gfx9_fimm32.rst b/llvm/docs/AMDGPU/gfx9_simm32_2.rst
similarity index 90%
rename from llvm/docs/AMDGPU/gfx9_fimm32.rst
rename to llvm/docs/AMDGPU/gfx9_simm32_2.rst
index 93507aedfb0a..8698c8a72250 100644
--- a/llvm/docs/AMDGPU/gfx9_fimm32.rst
+++ b/llvm/docs/AMDGPU/gfx9_simm32_2.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_fimm32:
+.. _amdgpu_synid_gfx9_simm32_2:
-imm32
-===========================
+simm32
+======
A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
The value is converted to *f32* as described :ref:`here<amdgpu_synid_fp_conv>`.
diff --git a/llvm/docs/AMDGPU/gfx9_offset_buf.rst b/llvm/docs/AMDGPU/gfx9_soffset.rst
similarity index 51%
rename from llvm/docs/AMDGPU/gfx9_offset_buf.rst
rename to llvm/docs/AMDGPU/gfx9_soffset.rst
index 7a01fde7f3c1..9b55558bb6e9 100644
--- a/llvm/docs/AMDGPU/gfx9_offset_buf.rst
+++ b/llvm/docs/AMDGPU/gfx9_soffset.rst
@@ -5,13 +5,13 @@
* *
**************************************************
-.. _amdgpu_synid9_offset_buf:
+.. _amdgpu_synid_gfx9_soffset:
soffset
-===========================
+=======
An unsigned byte offset.
*Size:* 1 dword.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx9_offset_smem_plain.rst b/llvm/docs/AMDGPU/gfx9_soffset_1.rst
similarity index 70%
rename from llvm/docs/AMDGPU/gfx9_offset_smem_plain.rst
rename to llvm/docs/AMDGPU/gfx9_soffset_1.rst
index a7f6867d863d..ecac0608d1c8 100644
--- a/llvm/docs/AMDGPU/gfx9_offset_smem_plain.rst
+++ b/llvm/docs/AMDGPU/gfx9_soffset_1.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_offset_smem_plain:
+.. _amdgpu_synid_gfx9_soffset_1:
soffset
-===========================
+=======
An offset added to the base address to get memory address.
@@ -17,4 +17,4 @@ An offset added to the base address to get memory address.
*Size:* 1 dword.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`simm21<amdgpu_synid_simm21>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`simm21<amdgpu_synid_simm21>`
diff --git a/llvm/docs/AMDGPU/gfx9_offset_smem_buf.rst b/llvm/docs/AMDGPU/gfx9_soffset_2.rst
similarity index 64%
rename from llvm/docs/AMDGPU/gfx9_offset_smem_buf.rst
rename to llvm/docs/AMDGPU/gfx9_soffset_2.rst
index 7c23cae0eb01..8faf02db065c 100644
--- a/llvm/docs/AMDGPU/gfx9_offset_smem_buf.rst
+++ b/llvm/docs/AMDGPU/gfx9_soffset_2.rst
@@ -5,13 +5,13 @@
* *
**************************************************
-.. _amdgpu_synid9_offset_smem_buf:
+.. _amdgpu_synid_gfx9_soffset_2:
soffset
-===========================
+=======
An unsigned 20-bit offset added to the base address to get memory address.
*Size:* 1 dword.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`uimm20<amdgpu_synid_uimm20>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`uimm20<amdgpu_synid_uimm20>`
diff --git a/llvm/docs/AMDGPU/gfx9_src.rst b/llvm/docs/AMDGPU/gfx9_src.rst
new file mode 100644
index 000000000000..f0fe23228f68
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx9_src.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx9_src:
+
+src
+===
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx9_src32_0.rst b/llvm/docs/AMDGPU/gfx9_src32_0.rst
deleted file mode 100644
index d4c495841c04..000000000000
--- a/llvm/docs/AMDGPU/gfx9_src32_0.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid9_src32_0:
-
-src
-===========================
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx9_src32_1.rst b/llvm/docs/AMDGPU/gfx9_src32_1.rst
deleted file mode 100644
index b65ec271a16a..000000000000
--- a/llvm/docs/AMDGPU/gfx9_src32_1.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid9_src32_1:
-
-src
-===========================
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx9_src32_2.rst b/llvm/docs/AMDGPU/gfx9_src32_2.rst
deleted file mode 100644
index cc306a913c63..000000000000
--- a/llvm/docs/AMDGPU/gfx9_src32_2.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid9_src32_2:
-
-src
-===========================
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx9_src32_3.rst b/llvm/docs/AMDGPU/gfx9_src32_3.rst
deleted file mode 100644
index 2f13457ea177..000000000000
--- a/llvm/docs/AMDGPU/gfx9_src32_3.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid9_src32_3:
-
-src
-===========================
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx9_src32_4.rst b/llvm/docs/AMDGPU/gfx9_src32_4.rst
deleted file mode 100644
index f146fe8065fd..000000000000
--- a/llvm/docs/AMDGPU/gfx9_src32_4.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid9_src32_4:
-
-src
-===========================
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx9_src32_5.rst b/llvm/docs/AMDGPU/gfx9_src32_5.rst
deleted file mode 100644
index 4ac258533daf..000000000000
--- a/llvm/docs/AMDGPU/gfx9_src32_5.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid9_src32_5:
-
-src
-===========================
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx9_src32_6.rst b/llvm/docs/AMDGPU/gfx9_src32_6.rst
deleted file mode 100644
index 42377cba7c23..000000000000
--- a/llvm/docs/AMDGPU/gfx9_src32_6.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid9_src32_6:
-
-src
-===========================
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`iconst<amdgpu_synid_iconst>`
diff --git a/llvm/docs/AMDGPU/gfx9_src32_7.rst b/llvm/docs/AMDGPU/gfx9_src32_7.rst
deleted file mode 100644
index 809cd04b60fe..000000000000
--- a/llvm/docs/AMDGPU/gfx9_src32_7.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid9_src32_7:
-
-src
-===========================
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`iconst<amdgpu_synid_iconst>`
diff --git a/llvm/docs/AMDGPU/gfx9_src64_0.rst b/llvm/docs/AMDGPU/gfx9_src64_0.rst
deleted file mode 100644
index cc6e5ca16565..000000000000
--- a/llvm/docs/AMDGPU/gfx9_src64_0.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid9_src64_0:
-
-src
-===========================
-
-Instruction input.
-
-*Size:* 2 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx9_ssrc64_2.rst b/llvm/docs/AMDGPU/gfx9_src_1.rst
similarity index 59%
rename from llvm/docs/AMDGPU/gfx9_ssrc64_2.rst
rename to llvm/docs/AMDGPU/gfx9_src_1.rst
index a9aa6dc8a4a3..ac4dea9107a7 100644
--- a/llvm/docs/AMDGPU/gfx9_ssrc64_2.rst
+++ b/llvm/docs/AMDGPU/gfx9_src_1.rst
@@ -5,13 +5,13 @@
* *
**************************************************
-.. _amdgpu_synid9_ssrc64_2:
+.. _amdgpu_synid_gfx9_src_1:
-ssrc
-===========================
+src
+===
Instruction input.
-*Size:* 2 dwords.
+*Size:* 1 dword.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx9_src_10.rst b/llvm/docs/AMDGPU/gfx9_src_10.rst
new file mode 100644
index 000000000000..9c46c019d5c6
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx9_src_10.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx9_src_10:
+
+src
+===
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`ival<amdgpu_synid_ival>`
diff --git a/llvm/docs/AMDGPU/gfx9_src_2.rst b/llvm/docs/AMDGPU/gfx9_src_2.rst
new file mode 100644
index 000000000000..a2a0b35f3ee0
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx9_src_2.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx9_src_2:
+
+src
+===
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx9_src_3.rst b/llvm/docs/AMDGPU/gfx9_src_3.rst
new file mode 100644
index 000000000000..7f2de41e458c
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx9_src_3.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx9_src_3:
+
+src
+===
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`ival<amdgpu_synid_ival>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx9_src_4.rst b/llvm/docs/AMDGPU/gfx9_src_4.rst
new file mode 100644
index 000000000000..d9c94428114d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx9_src_4.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx9_src_4:
+
+src
+===
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`ival<amdgpu_synid_ival>`
diff --git a/llvm/docs/AMDGPU/gfx9_vsrc32_1.rst b/llvm/docs/AMDGPU/gfx9_src_5.rst
similarity index 86%
rename from llvm/docs/AMDGPU/gfx9_vsrc32_1.rst
rename to llvm/docs/AMDGPU/gfx9_src_5.rst
index 5a5b9218e160..acbac62e7bd3 100644
--- a/llvm/docs/AMDGPU/gfx9_vsrc32_1.rst
+++ b/llvm/docs/AMDGPU/gfx9_src_5.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_vsrc32_1:
+.. _amdgpu_synid_gfx9_src_5:
-vsrc
-===========================
+src
+===
Instruction input.
diff --git a/llvm/docs/AMDGPU/gfx9_src_6.rst b/llvm/docs/AMDGPU/gfx9_src_6.rst
new file mode 100644
index 000000000000..ebae6c088342
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx9_src_6.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx9_src_6:
+
+src
+===
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`ival<amdgpu_synid_ival>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx9_ssrc64_0.rst b/llvm/docs/AMDGPU/gfx9_src_7.rst
similarity index 61%
rename from llvm/docs/AMDGPU/gfx9_ssrc64_0.rst
rename to llvm/docs/AMDGPU/gfx9_src_7.rst
index 4a3ef065a9b5..2b736f8e86e8 100644
--- a/llvm/docs/AMDGPU/gfx9_ssrc64_0.rst
+++ b/llvm/docs/AMDGPU/gfx9_src_7.rst
@@ -5,13 +5,13 @@
* *
**************************************************
-.. _amdgpu_synid9_ssrc64_0:
+.. _amdgpu_synid_gfx9_src_7:
-ssrc
-===========================
+src
+===
Instruction input.
-*Size:* 2 dwords.
+*Size:* 1 dword.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx9_src_8.rst b/llvm/docs/AMDGPU/gfx9_src_8.rst
new file mode 100644
index 000000000000..f610fc23125d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx9_src_8.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx9_src_8:
+
+src
+===
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx9_src64_1.rst b/llvm/docs/AMDGPU/gfx9_src_9.rst
similarity index 51%
rename from llvm/docs/AMDGPU/gfx9_src64_1.rst
rename to llvm/docs/AMDGPU/gfx9_src_9.rst
index 9075c24085f3..83cb0b4c3e1b 100644
--- a/llvm/docs/AMDGPU/gfx9_src64_1.rst
+++ b/llvm/docs/AMDGPU/gfx9_src_9.rst
@@ -5,13 +5,13 @@
* *
**************************************************
-.. _amdgpu_synid9_src64_1:
+.. _amdgpu_synid_gfx9_src_9:
src
-===========================
+===
Instruction input.
*Size:* 2 dwords.
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx9_rsrc_mimg.rst b/llvm/docs/AMDGPU/gfx9_srsrc.rst
similarity index 89%
rename from llvm/docs/AMDGPU/gfx9_rsrc_mimg.rst
rename to llvm/docs/AMDGPU/gfx9_srsrc.rst
index 29c90a14b8a7..5916602cb100 100644
--- a/llvm/docs/AMDGPU/gfx9_rsrc_mimg.rst
+++ b/llvm/docs/AMDGPU/gfx9_srsrc.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_rsrc_mimg:
+.. _amdgpu_synid_gfx9_srsrc:
srsrc
-===========================
+=====
Image resource constant which defines the location of the image buffer in memory, its dimensions, tiling, and data format.
diff --git a/llvm/docs/AMDGPU/gfx9_rsrc_buf.rst b/llvm/docs/AMDGPU/gfx9_srsrc_1.rst
similarity index 89%
rename from llvm/docs/AMDGPU/gfx9_rsrc_buf.rst
rename to llvm/docs/AMDGPU/gfx9_srsrc_1.rst
index 3dc17753d612..4cbcb1fb8298 100644
--- a/llvm/docs/AMDGPU/gfx9_rsrc_buf.rst
+++ b/llvm/docs/AMDGPU/gfx9_srsrc_1.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_rsrc_buf:
+.. _amdgpu_synid_gfx9_srsrc_1:
srsrc
-===========================
+=====
Buffer resource constant which defines the address and characteristics of the buffer in memory.
diff --git a/llvm/docs/AMDGPU/gfx9_samp_mimg.rst b/llvm/docs/AMDGPU/gfx9_ssamp.rst
similarity index 89%
rename from llvm/docs/AMDGPU/gfx9_samp_mimg.rst
rename to llvm/docs/AMDGPU/gfx9_ssamp.rst
index f901142909bb..ae8ba80473bb 100644
--- a/llvm/docs/AMDGPU/gfx9_samp_mimg.rst
+++ b/llvm/docs/AMDGPU/gfx9_ssamp.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_samp_mimg:
+.. _amdgpu_synid_gfx9_ssamp:
ssamp
-===========================
+=====
Sampler constant used to specify filtering options applied to the image data after it is read.
diff --git a/llvm/docs/AMDGPU/gfx9_ssrc.rst b/llvm/docs/AMDGPU/gfx9_ssrc.rst
new file mode 100644
index 000000000000..59f44c6a9346
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx9_ssrc.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx9_ssrc:
+
+ssrc
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx9_ssrc32_0.rst b/llvm/docs/AMDGPU/gfx9_ssrc32_0.rst
deleted file mode 100644
index d52f6880b713..000000000000
--- a/llvm/docs/AMDGPU/gfx9_ssrc32_0.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid9_ssrc32_0:
-
-ssrc
-===========================
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx9_ssrc32_4.rst b/llvm/docs/AMDGPU/gfx9_ssrc32_4.rst
deleted file mode 100644
index b151fbb1bd15..000000000000
--- a/llvm/docs/AMDGPU/gfx9_ssrc32_4.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid9_ssrc32_4:
-
-ssrc
-===========================
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx9_ssrc_1.rst b/llvm/docs/AMDGPU/gfx9_ssrc_1.rst
new file mode 100644
index 000000000000..6fd4eafb60ac
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx9_ssrc_1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx9_ssrc_1:
+
+ssrc
+====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx9_ssrc32_1.rst b/llvm/docs/AMDGPU/gfx9_ssrc_2.rst
similarity index 69%
rename from llvm/docs/AMDGPU/gfx9_ssrc32_1.rst
rename to llvm/docs/AMDGPU/gfx9_ssrc_2.rst
index caea76406614..60a15bbab089 100644
--- a/llvm/docs/AMDGPU/gfx9_ssrc32_1.rst
+++ b/llvm/docs/AMDGPU/gfx9_ssrc_2.rst
@@ -5,13 +5,13 @@
* *
**************************************************
-.. _amdgpu_synid9_ssrc32_1:
+.. _amdgpu_synid_gfx9_ssrc_2:
ssrc
-===========================
+====
Instruction input.
*Size:* 1 dword.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx9_ssrc64_1.rst b/llvm/docs/AMDGPU/gfx9_ssrc_3.rst
similarity index 69%
rename from llvm/docs/AMDGPU/gfx9_ssrc64_1.rst
rename to llvm/docs/AMDGPU/gfx9_ssrc_3.rst
index 02be6c537b72..98b002065aa6 100644
--- a/llvm/docs/AMDGPU/gfx9_ssrc64_1.rst
+++ b/llvm/docs/AMDGPU/gfx9_ssrc_3.rst
@@ -5,13 +5,13 @@
* *
**************************************************
-.. _amdgpu_synid9_ssrc64_1:
+.. _amdgpu_synid_gfx9_ssrc_3:
ssrc
-===========================
+====
Instruction input.
*Size:* 2 dwords.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx9_ssrc_4.rst b/llvm/docs/AMDGPU/gfx9_ssrc_4.rst
new file mode 100644
index 000000000000..a5a60d3c4097
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx9_ssrc_4.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx9_ssrc_4:
+
+ssrc
+====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx9_ssrc64_3.rst b/llvm/docs/AMDGPU/gfx9_ssrc_5.rst
similarity index 65%
rename from llvm/docs/AMDGPU/gfx9_ssrc64_3.rst
rename to llvm/docs/AMDGPU/gfx9_ssrc_5.rst
index 3414802295ad..bd0dcfd16871 100644
--- a/llvm/docs/AMDGPU/gfx9_ssrc64_3.rst
+++ b/llvm/docs/AMDGPU/gfx9_ssrc_5.rst
@@ -5,13 +5,13 @@
* *
**************************************************
-.. _amdgpu_synid9_ssrc64_3:
+.. _amdgpu_synid_gfx9_ssrc_5:
ssrc
-===========================
+====
Instruction input.
*Size:* 2 dwords.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`
diff --git a/llvm/docs/AMDGPU/gfx9_ssrc32_2.rst b/llvm/docs/AMDGPU/gfx9_ssrc_6.rst
similarity index 62%
rename from llvm/docs/AMDGPU/gfx9_ssrc32_2.rst
rename to llvm/docs/AMDGPU/gfx9_ssrc_6.rst
index 034f20e30ee9..02faee4dc6fe 100644
--- a/llvm/docs/AMDGPU/gfx9_ssrc32_2.rst
+++ b/llvm/docs/AMDGPU/gfx9_ssrc_6.rst
@@ -5,13 +5,13 @@
* *
**************************************************
-.. _amdgpu_synid9_ssrc32_2:
+.. _amdgpu_synid_gfx9_ssrc_6:
ssrc
-===========================
+====
Instruction input.
*Size:* 1 dword.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`
diff --git a/llvm/docs/AMDGPU/gfx9_ssrc32_3.rst b/llvm/docs/AMDGPU/gfx9_ssrc_7.rst
similarity index 62%
rename from llvm/docs/AMDGPU/gfx9_ssrc32_3.rst
rename to llvm/docs/AMDGPU/gfx9_ssrc_7.rst
index 1b08cad751d8..ed05b75f75dc 100644
--- a/llvm/docs/AMDGPU/gfx9_ssrc32_3.rst
+++ b/llvm/docs/AMDGPU/gfx9_ssrc_7.rst
@@ -5,13 +5,13 @@
* *
**************************************************
-.. _amdgpu_synid9_ssrc32_3:
+.. _amdgpu_synid_gfx9_ssrc_7:
ssrc
-===========================
+====
Instruction input.
*Size:* 1 dword.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`iconst<amdgpu_synid_iconst>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`iconst<amdgpu_synid_iconst>`
diff --git a/llvm/docs/AMDGPU/gfx9_ssrc_8.rst b/llvm/docs/AMDGPU/gfx9_ssrc_8.rst
new file mode 100644
index 000000000000..8457952c0253
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx9_ssrc_8.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx9_ssrc_8:
+
+ssrc
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx9_tgt.rst b/llvm/docs/AMDGPU/gfx9_tgt.rst
index 066a2f3dfb9c..bb8e98667775 100644
--- a/llvm/docs/AMDGPU/gfx9_tgt.rst
+++ b/llvm/docs/AMDGPU/gfx9_tgt.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_tgt:
+.. _amdgpu_synid_gfx9_tgt:
tgt
-===========================
+===
An export target:
diff --git a/llvm/docs/AMDGPU/gfx9_type_dev.rst b/llvm/docs/AMDGPU/gfx9_type_deviation.rst
similarity index 85%
rename from llvm/docs/AMDGPU/gfx9_type_dev.rst
rename to llvm/docs/AMDGPU/gfx9_type_deviation.rst
index 7dc86096d412..47a5874a29c9 100644
--- a/llvm/docs/AMDGPU/gfx9_type_dev.rst
+++ b/llvm/docs/AMDGPU/gfx9_type_deviation.rst
@@ -5,9 +5,9 @@
* *
**************************************************
-.. _amdgpu_synid9_type_dev:
+.. _amdgpu_synid_gfx9_type_deviation:
-Type deviation
-===========================
+Type Deviation
+==============
*Type* of this operand
diff ers from *type* :ref:`implied by the opcode<amdgpu_syn_instruction_type>`. This tag specifies actual operand *type*.
diff --git a/llvm/docs/AMDGPU/gfx9_addr_ds.rst b/llvm/docs/AMDGPU/gfx9_vaddr.rst
similarity index 87%
rename from llvm/docs/AMDGPU/gfx9_addr_ds.rst
rename to llvm/docs/AMDGPU/gfx9_vaddr.rst
index 11742462b946..194b2688f936 100644
--- a/llvm/docs/AMDGPU/gfx9_addr_ds.rst
+++ b/llvm/docs/AMDGPU/gfx9_vaddr.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_addr_ds:
+.. _amdgpu_synid_gfx9_vaddr:
vaddr
-===========================
+=====
An offset from the start of GDS/LDS memory.
diff --git a/llvm/docs/AMDGPU/gfx9_addr_flat.rst b/llvm/docs/AMDGPU/gfx9_vaddr_1.rst
similarity index 86%
rename from llvm/docs/AMDGPU/gfx9_addr_flat.rst
rename to llvm/docs/AMDGPU/gfx9_vaddr_1.rst
index c748d07090ec..aabf5655f058 100644
--- a/llvm/docs/AMDGPU/gfx9_addr_flat.rst
+++ b/llvm/docs/AMDGPU/gfx9_vaddr_1.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_addr_flat:
+.. _amdgpu_synid_gfx9_vaddr_1:
vaddr
-===========================
+=====
A 64-bit flat address.
diff --git a/llvm/docs/AMDGPU/gfx9_vaddr_2.rst b/llvm/docs/AMDGPU/gfx9_vaddr_2.rst
new file mode 100644
index 000000000000..0ee1edd2d9dd
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx9_vaddr_2.rst
@@ -0,0 +1,20 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx9_vaddr_2:
+
+vaddr
+=====
+
+A 64-bit flat global address or a 32-bit offset depending on addressing mode:
+
+* Address = :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>` + :ref:`offset13s<amdgpu_synid_flat_offset13s>`. :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>` is a 64-bit address. This mode is indicated by :ref:`saddr<amdgpu_synid_gfx9_saddr>` set to :ref:`off<amdgpu_synid_off>`.
+* Address = :ref:`saddr<amdgpu_synid_gfx9_saddr>` + :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>` + :ref:`offset13s<amdgpu_synid_flat_offset13s>`. :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>` is a 32-bit offset. This mode is used when :ref:`saddr<amdgpu_synid_gfx9_saddr>` is not :ref:`off<amdgpu_synid_off>`.
+
+*Size:* 1 or 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx9_vaddr_flat_scratch.rst b/llvm/docs/AMDGPU/gfx9_vaddr_3.rst
similarity index 72%
rename from llvm/docs/AMDGPU/gfx9_vaddr_flat_scratch.rst
rename to llvm/docs/AMDGPU/gfx9_vaddr_3.rst
index a72cf0662f42..f332cb6151ca 100644
--- a/llvm/docs/AMDGPU/gfx9_vaddr_flat_scratch.rst
+++ b/llvm/docs/AMDGPU/gfx9_vaddr_3.rst
@@ -5,14 +5,14 @@
* *
**************************************************
-.. _amdgpu_synid9_vaddr_flat_scratch:
+.. _amdgpu_synid_gfx9_vaddr_3:
vaddr
-===========================
+=====
An optional 32-bit flat scratch offset. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
-Either this operand or :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` must be set to :ref:`off<amdgpu_synid_off>`.
+Either this operand or :ref:`saddr<amdgpu_synid_gfx9_saddr_1>` must be set to :ref:`off<amdgpu_synid_off>`.
*Size:* 1 dword.
diff --git a/llvm/docs/AMDGPU/gfx9_addr_mimg.rst b/llvm/docs/AMDGPU/gfx9_vaddr_4.rst
similarity index 93%
rename from llvm/docs/AMDGPU/gfx9_addr_mimg.rst
rename to llvm/docs/AMDGPU/gfx9_vaddr_4.rst
index eb6ca882b6af..ccee5f4c4934 100644
--- a/llvm/docs/AMDGPU/gfx9_addr_mimg.rst
+++ b/llvm/docs/AMDGPU/gfx9_vaddr_4.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_addr_mimg:
+.. _amdgpu_synid_gfx9_vaddr_4:
vaddr
-===========================
+=====
Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.
diff --git a/llvm/docs/AMDGPU/gfx9_addr_buf.rst b/llvm/docs/AMDGPU/gfx9_vaddr_5.rst
similarity index 94%
rename from llvm/docs/AMDGPU/gfx9_addr_buf.rst
rename to llvm/docs/AMDGPU/gfx9_vaddr_5.rst
index c253640fa5fb..0c2b159f826e 100644
--- a/llvm/docs/AMDGPU/gfx9_addr_buf.rst
+++ b/llvm/docs/AMDGPU/gfx9_vaddr_5.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_addr_buf:
+.. _amdgpu_synid_gfx9_vaddr_5:
vaddr
-===========================
+=====
This is an optional operand which may specify offset and/or index.
diff --git a/llvm/docs/AMDGPU/gfx9_vaddr_flat_global.rst b/llvm/docs/AMDGPU/gfx9_vaddr_flat_global.rst
deleted file mode 100644
index 0ecd151edbb0..000000000000
--- a/llvm/docs/AMDGPU/gfx9_vaddr_flat_global.rst
+++ /dev/null
@@ -1,20 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid9_vaddr_flat_global:
-
-vaddr
-===========================
-
-A 64-bit flat global address or a 32-bit offset depending on addressing mode:
-
-* Address = :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>` + :ref:`offset13s<amdgpu_synid_flat_offset13s>`. :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>` is a 64-bit address. This mode is indicated by :ref:`saddr<amdgpu_synid9_saddr_flat_global>` set to :ref:`off<amdgpu_synid_off>`.
-* Address = :ref:`saddr<amdgpu_synid9_saddr_flat_global>` + :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>` + :ref:`offset13s<amdgpu_synid_flat_offset13s>`. :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>` is a 32-bit offset. This mode is used when :ref:`saddr<amdgpu_synid9_saddr_flat_global>` is not :ref:`off<amdgpu_synid_off>`.
-
-*Size:* 1 or 2 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx9_vcc_64.rst b/llvm/docs/AMDGPU/gfx9_vcc.rst
similarity index 87%
rename from llvm/docs/AMDGPU/gfx9_vcc_64.rst
rename to llvm/docs/AMDGPU/gfx9_vcc.rst
index 788306b2a5e4..beda47e44516 100644
--- a/llvm/docs/AMDGPU/gfx9_vcc_64.rst
+++ b/llvm/docs/AMDGPU/gfx9_vcc.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_vcc_64:
+.. _amdgpu_synid_gfx9_vcc:
vcc
-===========================
+===
Vector condition code.
diff --git a/llvm/docs/AMDGPU/gfx9_vdata32_0.rst b/llvm/docs/AMDGPU/gfx9_vdata.rst
similarity index 86%
rename from llvm/docs/AMDGPU/gfx9_vdata32_0.rst
rename to llvm/docs/AMDGPU/gfx9_vdata.rst
index e2857695acfb..fa754016904a 100644
--- a/llvm/docs/AMDGPU/gfx9_vdata32_0.rst
+++ b/llvm/docs/AMDGPU/gfx9_vdata.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_vdata32_0:
+.. _amdgpu_synid_gfx9_vdata:
vdata
-===========================
+=====
Instruction input.
diff --git a/llvm/docs/AMDGPU/gfx9_vdata0.rst b/llvm/docs/AMDGPU/gfx9_vdata0.rst
new file mode 100644
index 000000000000..4df069ff9ffd
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx9_vdata0.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx9_vdata0:
+
+vdata0
+======
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx9_vdata0_1.rst b/llvm/docs/AMDGPU/gfx9_vdata0_1.rst
new file mode 100644
index 000000000000..00595e258f04
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx9_vdata0_1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx9_vdata0_1:
+
+vdata0
+======
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx9_vdata1.rst b/llvm/docs/AMDGPU/gfx9_vdata1.rst
new file mode 100644
index 000000000000..07e21e3ddcfc
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx9_vdata1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx9_vdata1:
+
+vdata1
+======
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx9_vdata1_1.rst b/llvm/docs/AMDGPU/gfx9_vdata1_1.rst
new file mode 100644
index 000000000000..a5083fb88291
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx9_vdata1_1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx9_vdata1_1:
+
+vdata1
+======
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx9_vdata64_0.rst b/llvm/docs/AMDGPU/gfx9_vdata_1.rst
similarity index 86%
rename from llvm/docs/AMDGPU/gfx9_vdata64_0.rst
rename to llvm/docs/AMDGPU/gfx9_vdata_1.rst
index fcd1d0f82708..585f816e3e3e 100644
--- a/llvm/docs/AMDGPU/gfx9_vdata64_0.rst
+++ b/llvm/docs/AMDGPU/gfx9_vdata_1.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_vdata64_0:
+.. _amdgpu_synid_gfx9_vdata_1:
vdata
-===========================
+=====
Instruction input.
diff --git a/llvm/docs/AMDGPU/gfx9_data_buf_atomic128.rst b/llvm/docs/AMDGPU/gfx9_vdata_10.rst
similarity index 89%
rename from llvm/docs/AMDGPU/gfx9_data_buf_atomic128.rst
rename to llvm/docs/AMDGPU/gfx9_vdata_10.rst
index 11c7c73479d2..2d420877eedf 100644
--- a/llvm/docs/AMDGPU/gfx9_data_buf_atomic128.rst
+++ b/llvm/docs/AMDGPU/gfx9_vdata_10.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_data_buf_atomic128:
+.. _amdgpu_synid_gfx9_vdata_10:
vdata
-===========================
+=====
Input data for an atomic instruction.
diff --git a/llvm/docs/AMDGPU/gfx9_vdata128_0.rst b/llvm/docs/AMDGPU/gfx9_vdata_2.rst
similarity index 86%
rename from llvm/docs/AMDGPU/gfx9_vdata128_0.rst
rename to llvm/docs/AMDGPU/gfx9_vdata_2.rst
index 3d2b4905fa3f..5cd172bfc7d5 100644
--- a/llvm/docs/AMDGPU/gfx9_vdata128_0.rst
+++ b/llvm/docs/AMDGPU/gfx9_vdata_2.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_vdata128_0:
+.. _amdgpu_synid_gfx9_vdata_2:
vdata
-===========================
+=====
Instruction input.
diff --git a/llvm/docs/AMDGPU/gfx9_vdata96_0.rst b/llvm/docs/AMDGPU/gfx9_vdata_3.rst
similarity index 86%
rename from llvm/docs/AMDGPU/gfx9_vdata96_0.rst
rename to llvm/docs/AMDGPU/gfx9_vdata_3.rst
index 8a8cb7647bce..a705537d155b 100644
--- a/llvm/docs/AMDGPU/gfx9_vdata96_0.rst
+++ b/llvm/docs/AMDGPU/gfx9_vdata_3.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_vdata96_0:
+.. _amdgpu_synid_gfx9_vdata_3:
vdata
-===========================
+=====
Instruction input.
diff --git a/llvm/docs/AMDGPU/gfx9_data_mimg_atomic_reg.rst b/llvm/docs/AMDGPU/gfx9_vdata_4.rst
similarity index 93%
rename from llvm/docs/AMDGPU/gfx9_data_mimg_atomic_reg.rst
rename to llvm/docs/AMDGPU/gfx9_vdata_4.rst
index 6889c468d26e..1d8eb16be775 100644
--- a/llvm/docs/AMDGPU/gfx9_data_mimg_atomic_reg.rst
+++ b/llvm/docs/AMDGPU/gfx9_vdata_4.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_data_mimg_atomic_reg:
+.. _amdgpu_synid_gfx9_vdata_4:
vdata
-===========================
+=====
Input data for an atomic instruction.
diff --git a/llvm/docs/AMDGPU/gfx9_data_mimg_atomic_cmp.rst b/llvm/docs/AMDGPU/gfx9_vdata_5.rst
similarity index 93%
rename from llvm/docs/AMDGPU/gfx9_data_mimg_atomic_cmp.rst
rename to llvm/docs/AMDGPU/gfx9_vdata_5.rst
index 79d10fdb4e96..1a9ee65b0d17 100644
--- a/llvm/docs/AMDGPU/gfx9_data_mimg_atomic_cmp.rst
+++ b/llvm/docs/AMDGPU/gfx9_vdata_5.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_data_mimg_atomic_cmp:
+.. _amdgpu_synid_gfx9_vdata_5:
vdata
-===========================
+=====
Input data for an atomic instruction.
@@ -23,5 +23,4 @@ Optionally may serve as an output data:
Note: the surface data format is indicated in the image resource constant but not in the instruction.
-
*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx9_data_mimg_store_d16.rst b/llvm/docs/AMDGPU/gfx9_vdata_6.rst
similarity index 91%
rename from llvm/docs/AMDGPU/gfx9_data_mimg_store_d16.rst
rename to llvm/docs/AMDGPU/gfx9_vdata_6.rst
index 5c521f80a49a..fab039c6757b 100644
--- a/llvm/docs/AMDGPU/gfx9_data_mimg_store_d16.rst
+++ b/llvm/docs/AMDGPU/gfx9_vdata_6.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_data_mimg_store_d16:
+.. _amdgpu_synid_gfx9_vdata_6:
vdata
-===========================
+=====
Image data to store by an *image_store* instruction.
@@ -17,5 +17,4 @@ Image data to store by an *image_store* instruction.
* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
* :ref:`d16<amdgpu_synid_d16>` specifies that data in registers are packed; each value occupies 16 bits.
-
*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx9_data_mimg_store.rst b/llvm/docs/AMDGPU/gfx9_vdata_7.rst
similarity index 88%
rename from llvm/docs/AMDGPU/gfx9_data_mimg_store.rst
rename to llvm/docs/AMDGPU/gfx9_vdata_7.rst
index 5e2b8b6a103c..df1dca53ba0e 100644
--- a/llvm/docs/AMDGPU/gfx9_data_mimg_store.rst
+++ b/llvm/docs/AMDGPU/gfx9_vdata_7.rst
@@ -5,14 +5,13 @@
* *
**************************************************
-.. _amdgpu_synid9_data_mimg_store:
+.. _amdgpu_synid_gfx9_vdata_7:
vdata
-===========================
+=====
Image data to store by an *image_store* instruction.
*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` which may specify from 1 to 4 data elements. Each data element occupies 1 dword.
-
*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx9_data_buf_atomic32.rst b/llvm/docs/AMDGPU/gfx9_vdata_8.rst
similarity index 89%
rename from llvm/docs/AMDGPU/gfx9_data_buf_atomic32.rst
rename to llvm/docs/AMDGPU/gfx9_vdata_8.rst
index 7b7d88b7a2d0..df9d32e69c45 100644
--- a/llvm/docs/AMDGPU/gfx9_data_buf_atomic32.rst
+++ b/llvm/docs/AMDGPU/gfx9_vdata_8.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_data_buf_atomic32:
+.. _amdgpu_synid_gfx9_vdata_8:
vdata
-===========================
+=====
Input data for an atomic instruction.
diff --git a/llvm/docs/AMDGPU/gfx9_data_buf_atomic64.rst b/llvm/docs/AMDGPU/gfx9_vdata_9.rst
similarity index 89%
rename from llvm/docs/AMDGPU/gfx9_data_buf_atomic64.rst
rename to llvm/docs/AMDGPU/gfx9_vdata_9.rst
index 71b2b4be2caf..caafea5beadd 100644
--- a/llvm/docs/AMDGPU/gfx9_data_buf_atomic64.rst
+++ b/llvm/docs/AMDGPU/gfx9_vdata_9.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_data_buf_atomic64:
+.. _amdgpu_synid_gfx9_vdata_9:
vdata
-===========================
+=====
Input data for an atomic instruction.
diff --git a/llvm/docs/AMDGPU/gfx9_vdst32_0.rst b/llvm/docs/AMDGPU/gfx9_vdst.rst
similarity index 86%
rename from llvm/docs/AMDGPU/gfx9_vdst32_0.rst
rename to llvm/docs/AMDGPU/gfx9_vdst.rst
index ccee55f7c106..1c003ac22fbc 100644
--- a/llvm/docs/AMDGPU/gfx9_vdst32_0.rst
+++ b/llvm/docs/AMDGPU/gfx9_vdst.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_vdst32_0:
+.. _amdgpu_synid_gfx9_vdst:
vdst
-===========================
+====
Instruction output.
diff --git a/llvm/docs/AMDGPU/gfx9_vdst64_0.rst b/llvm/docs/AMDGPU/gfx9_vdst_1.rst
similarity index 86%
rename from llvm/docs/AMDGPU/gfx9_vdst64_0.rst
rename to llvm/docs/AMDGPU/gfx9_vdst_1.rst
index 60bf384f2c11..7e2f6317ef3e 100644
--- a/llvm/docs/AMDGPU/gfx9_vdst64_0.rst
+++ b/llvm/docs/AMDGPU/gfx9_vdst_1.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_vdst64_0:
+.. _amdgpu_synid_gfx9_vdst_1:
vdst
-===========================
+====
Instruction output.
diff --git a/llvm/docs/AMDGPU/gfx9_dst_buf_64.rst b/llvm/docs/AMDGPU/gfx9_vdst_10.rst
similarity index 88%
rename from llvm/docs/AMDGPU/gfx9_dst_buf_64.rst
rename to llvm/docs/AMDGPU/gfx9_vdst_10.rst
index 6e27264ffe35..8e7b9908aa5a 100644
--- a/llvm/docs/AMDGPU/gfx9_dst_buf_64.rst
+++ b/llvm/docs/AMDGPU/gfx9_vdst_10.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_dst_buf_64:
+.. _amdgpu_synid_gfx9_vdst_10:
vdst
-===========================
+====
Instruction output: data read from a memory buffer.
diff --git a/llvm/docs/AMDGPU/gfx9_dst_buf_96.rst b/llvm/docs/AMDGPU/gfx9_vdst_11.rst
similarity index 88%
rename from llvm/docs/AMDGPU/gfx9_dst_buf_96.rst
rename to llvm/docs/AMDGPU/gfx9_vdst_11.rst
index 8011edc0cb1b..f3512d3aa21e 100644
--- a/llvm/docs/AMDGPU/gfx9_dst_buf_96.rst
+++ b/llvm/docs/AMDGPU/gfx9_vdst_11.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_dst_buf_96:
+.. _amdgpu_synid_gfx9_vdst_11:
vdst
-===========================
+====
Instruction output: data read from a memory buffer.
diff --git a/llvm/docs/AMDGPU/gfx9_dst_buf_128.rst b/llvm/docs/AMDGPU/gfx9_vdst_12.rst
similarity index 88%
rename from llvm/docs/AMDGPU/gfx9_dst_buf_128.rst
rename to llvm/docs/AMDGPU/gfx9_vdst_12.rst
index 691be0f69fe2..09d4d7a1bb53 100644
--- a/llvm/docs/AMDGPU/gfx9_dst_buf_128.rst
+++ b/llvm/docs/AMDGPU/gfx9_vdst_12.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_dst_buf_128:
+.. _amdgpu_synid_gfx9_vdst_12:
vdst
-===========================
+====
Instruction output: data read from a memory buffer.
diff --git a/llvm/docs/AMDGPU/gfx9_dst_buf_lds.rst b/llvm/docs/AMDGPU/gfx9_vdst_13.rst
similarity index 92%
rename from llvm/docs/AMDGPU/gfx9_dst_buf_lds.rst
rename to llvm/docs/AMDGPU/gfx9_vdst_13.rst
index 0445619d6408..ff27ff0d0d18 100644
--- a/llvm/docs/AMDGPU/gfx9_dst_buf_lds.rst
+++ b/llvm/docs/AMDGPU/gfx9_vdst_13.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_dst_buf_lds:
+.. _amdgpu_synid_gfx9_vdst_13:
vdst
-===========================
+====
Instruction output: data read from a memory buffer.
diff --git a/llvm/docs/AMDGPU/gfx9_vdst128_0.rst b/llvm/docs/AMDGPU/gfx9_vdst_2.rst
similarity index 86%
rename from llvm/docs/AMDGPU/gfx9_vdst128_0.rst
rename to llvm/docs/AMDGPU/gfx9_vdst_2.rst
index b8bbf89c2729..11c1fdbbecdd 100644
--- a/llvm/docs/AMDGPU/gfx9_vdst128_0.rst
+++ b/llvm/docs/AMDGPU/gfx9_vdst_2.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_vdst128_0:
+.. _amdgpu_synid_gfx9_vdst_2:
vdst
-===========================
+====
Instruction output.
diff --git a/llvm/docs/AMDGPU/gfx9_vdst96_0.rst b/llvm/docs/AMDGPU/gfx9_vdst_3.rst
similarity index 86%
rename from llvm/docs/AMDGPU/gfx9_vdst96_0.rst
rename to llvm/docs/AMDGPU/gfx9_vdst_3.rst
index 834d32a4387c..cfc129198c0e 100644
--- a/llvm/docs/AMDGPU/gfx9_vdst96_0.rst
+++ b/llvm/docs/AMDGPU/gfx9_vdst_3.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_vdst96_0:
+.. _amdgpu_synid_gfx9_vdst_3:
vdst
-===========================
+====
Instruction output.
diff --git a/llvm/docs/AMDGPU/gfx9_dst_flat_atomic32.rst b/llvm/docs/AMDGPU/gfx9_vdst_4.rst
similarity index 88%
rename from llvm/docs/AMDGPU/gfx9_dst_flat_atomic32.rst
rename to llvm/docs/AMDGPU/gfx9_vdst_4.rst
index 94a7fdac9703..b7d5ebef61ac 100644
--- a/llvm/docs/AMDGPU/gfx9_dst_flat_atomic32.rst
+++ b/llvm/docs/AMDGPU/gfx9_vdst_4.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_dst_flat_atomic32:
+.. _amdgpu_synid_gfx9_vdst_4:
vdst
-===========================
+====
Data returned by a 32-bit atomic flat instruction.
diff --git a/llvm/docs/AMDGPU/gfx9_dst_flat_atomic64.rst b/llvm/docs/AMDGPU/gfx9_vdst_5.rst
similarity index 88%
rename from llvm/docs/AMDGPU/gfx9_dst_flat_atomic64.rst
rename to llvm/docs/AMDGPU/gfx9_vdst_5.rst
index 7f684a7165e4..faf7f8d86d5a 100644
--- a/llvm/docs/AMDGPU/gfx9_dst_flat_atomic64.rst
+++ b/llvm/docs/AMDGPU/gfx9_vdst_5.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_dst_flat_atomic64:
+.. _amdgpu_synid_gfx9_vdst_5:
vdst
-===========================
+====
Data returned by a 64-bit atomic flat instruction.
diff --git a/llvm/docs/AMDGPU/gfx9_dst_mimg_gather4.rst b/llvm/docs/AMDGPU/gfx9_vdst_6.rst
similarity index 92%
rename from llvm/docs/AMDGPU/gfx9_dst_mimg_gather4.rst
rename to llvm/docs/AMDGPU/gfx9_vdst_6.rst
index 3bb6f30811f1..d82c8989c5cb 100644
--- a/llvm/docs/AMDGPU/gfx9_dst_mimg_gather4.rst
+++ b/llvm/docs/AMDGPU/gfx9_vdst_6.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_dst_mimg_gather4:
+.. _amdgpu_synid_gfx9_vdst_6:
vdst
-===========================
+====
Image data to load by an *image_gather4* instruction.
diff --git a/llvm/docs/AMDGPU/gfx9_dst_mimg_regular.rst b/llvm/docs/AMDGPU/gfx9_vdst_7.rst
similarity index 90%
rename from llvm/docs/AMDGPU/gfx9_dst_mimg_regular.rst
rename to llvm/docs/AMDGPU/gfx9_vdst_7.rst
index 1a7b848c1ee9..6c4860c9bf80 100644
--- a/llvm/docs/AMDGPU/gfx9_dst_mimg_regular.rst
+++ b/llvm/docs/AMDGPU/gfx9_vdst_7.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_dst_mimg_regular:
+.. _amdgpu_synid_gfx9_vdst_7:
vdst
-===========================
+====
Image data to load by an image instruction.
diff --git a/llvm/docs/AMDGPU/gfx9_dst_mimg_regular_d16.rst b/llvm/docs/AMDGPU/gfx9_vdst_8.rst
similarity index 92%
rename from llvm/docs/AMDGPU/gfx9_dst_mimg_regular_d16.rst
rename to llvm/docs/AMDGPU/gfx9_vdst_8.rst
index a155639bf3e6..4a507b19372f 100644
--- a/llvm/docs/AMDGPU/gfx9_dst_mimg_regular_d16.rst
+++ b/llvm/docs/AMDGPU/gfx9_vdst_8.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_dst_mimg_regular_d16:
+.. _amdgpu_synid_gfx9_vdst_8:
vdst
-===========================
+====
Image data to load by an image instruction.
@@ -18,5 +18,4 @@ Image data to load by an image instruction.
* :ref:`d16<amdgpu_synid_d16>` specifies that data elements in registers are packed; each value occupies 16 bits.
* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
-
*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx9_dst_buf_32.rst b/llvm/docs/AMDGPU/gfx9_vdst_9.rst
similarity index 88%
rename from llvm/docs/AMDGPU/gfx9_dst_buf_32.rst
rename to llvm/docs/AMDGPU/gfx9_vdst_9.rst
index 5ee1aa2c0c6e..dabefd27c168 100644
--- a/llvm/docs/AMDGPU/gfx9_dst_buf_32.rst
+++ b/llvm/docs/AMDGPU/gfx9_vdst_9.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_dst_buf_32:
+.. _amdgpu_synid_gfx9_vdst_9:
vdst
-===========================
+====
Instruction output: data read from a memory buffer.
diff --git a/llvm/docs/AMDGPU/gfx9_src_exp.rst b/llvm/docs/AMDGPU/gfx9_vsrc.rst
similarity index 94%
rename from llvm/docs/AMDGPU/gfx9_src_exp.rst
rename to llvm/docs/AMDGPU/gfx9_vsrc.rst
index 91a5d53b92ba..efe436c9485c 100644
--- a/llvm/docs/AMDGPU/gfx9_src_exp.rst
+++ b/llvm/docs/AMDGPU/gfx9_vsrc.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_src_exp:
+.. _amdgpu_synid_gfx9_vsrc:
vsrc
-===========================
+====
Data to copy to export buffers. This is an optional operand. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
diff --git a/llvm/docs/AMDGPU/gfx9_vsrc32_0.rst b/llvm/docs/AMDGPU/gfx9_vsrc_1.rst
similarity index 86%
rename from llvm/docs/AMDGPU/gfx9_vsrc32_0.rst
rename to llvm/docs/AMDGPU/gfx9_vsrc_1.rst
index a056f3a1dffb..15035b4d3e57 100644
--- a/llvm/docs/AMDGPU/gfx9_vsrc32_0.rst
+++ b/llvm/docs/AMDGPU/gfx9_vsrc_1.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_vsrc32_0:
+.. _amdgpu_synid_gfx9_vsrc_1:
vsrc
-===========================
+====
Instruction input.
diff --git a/llvm/docs/AMDGPU/gfx9_vsrc128_0.rst b/llvm/docs/AMDGPU/gfx9_vsrc_2.rst
similarity index 86%
rename from llvm/docs/AMDGPU/gfx9_vsrc128_0.rst
rename to llvm/docs/AMDGPU/gfx9_vsrc_2.rst
index 3e8c6dedf5d5..3eb9e5fb5b36 100644
--- a/llvm/docs/AMDGPU/gfx9_vsrc128_0.rst
+++ b/llvm/docs/AMDGPU/gfx9_vsrc_2.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_vsrc128_0:
+.. _amdgpu_synid_gfx9_vsrc_2:
vsrc
-===========================
+====
Instruction input.
diff --git a/llvm/docs/AMDGPU/gfx9_vsrc64_0.rst b/llvm/docs/AMDGPU/gfx9_vsrc_3.rst
similarity index 86%
rename from llvm/docs/AMDGPU/gfx9_vsrc64_0.rst
rename to llvm/docs/AMDGPU/gfx9_vsrc_3.rst
index b91b3405c1db..886257f20c83 100644
--- a/llvm/docs/AMDGPU/gfx9_vsrc64_0.rst
+++ b/llvm/docs/AMDGPU/gfx9_vsrc_3.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_vsrc64_0:
+.. _amdgpu_synid_gfx9_vsrc_3:
vsrc
-===========================
+====
Instruction input.
diff --git a/llvm/docs/AMDGPU/gfx9_waitcnt.rst b/llvm/docs/AMDGPU/gfx9_waitcnt.rst
index 73c0b6331544..81e2cb4d06e6 100644
--- a/llvm/docs/AMDGPU/gfx9_waitcnt.rst
+++ b/llvm/docs/AMDGPU/gfx9_waitcnt.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid9_waitcnt:
+.. _amdgpu_synid_gfx9_waitcnt:
waitcnt
-===========================
+=======
Counts of outstanding instructions to wait for.
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