[PATCH] D106633: [RISCV][Docs] Add description about inline asm constraint for V.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai created this revision.
HsiangKai added reviewers: craig.topper, khchen, kito-cheng, frasercrmck, rogfer01.
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Add constraint 'v' in LLVM IR for vector registers and 'vr' and 'vm' for
C/C++ inline asm constraints.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D106633

Files:
  llvm/docs/LangRef.rst


Index: llvm/docs/LangRef.rst
===================================================================
--- llvm/docs/LangRef.rst
+++ llvm/docs/LangRef.rst
@@ -4767,6 +4767,8 @@
 - ``f``: A 32- or 64-bit floating-point register (requires F or D extension).
 - ``r``: A 32- or 64-bit general-purpose register (depending on the platform
   ``XLEN``).
+- ``v``: A vector register. Clang uses ``vr`` for vector registers and ``vm``
+  for vector mask registers. (requires V extension).
 
 Sparc:
 


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