[PATCH] D106602: Add tablegen definition for the Find Leading Set (FLS) instruction for the ARC backend

[Thomas Johnson via Phabricator via llvm-commits]

thomasjohns created this revision.
thomasjohns added a reviewer: marksl.
Herald added a subscriber: hiraditya.
thomasjohns requested review of this revision.
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This adds an entry for the FLS instruction to tablegen and demonstrates the ability to decode this instruction from an object file.

For example, when disassembling the object file derived from compiling:

  int f(int x) {
    return __builtin_clz(x);
  }

we used to have:

  00000000 <f>:
         0: 2f 28 13 80   <unknown>
         4: ca 20 21 08   mov.eq  %r0, 32
         8: e0 7f         j_s.d   [%blink]
         a: ce 20 e2 07   rsub.ne %r0, %r0, 31

but now we have:

  00000000 <f>:
         0: 2f 28 13 80   fls.f   %r0, %r0
         4: ca 20 21 08   mov.eq  %r0, 32
         8: e0 7f         j_s.d   [%blink]
         a: ce 20 e2 07   rsub.ne %r0, %r0, 31


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D106602

Files:
  llvm/lib/Target/ARC/ARCInstrInfo.td
  llvm/test/MC/Disassembler/ARC/misc.txt


Index: llvm/test/MC/Disassembler/ARC/misc.txt
===================================================================
--- llvm/test/MC/Disassembler/ARC/misc.txt
+++ llvm/test/MC/Disassembler/ARC/misc.txt
@@ -54,3 +54,9 @@
 
 # CHECK: seteq %fp, %fp, -1
 0xb8 0x23 0xff 0x3f 
+
+# CHECK: fls %r0, %r0
+0x2f 0x28 0x13 0x00
+
+# CHECK: fls.f %r0, %r0
+0x2f 0x28 0x13 0x80
Index: llvm/lib/Target/ARC/ARCInstrInfo.td
===================================================================
--- llvm/lib/Target/ARC/ARCInstrInfo.td
+++ llvm/lib/Target/ARC/ARCInstrInfo.td
@@ -224,6 +224,8 @@
 
 multiclass ArcUnaryGEN4Inst<bits<6> mincode, string opasm> :
   ArcUnaryInst<0b00100, mincode, opasm>;
+multiclass ArcUnaryEXT5Inst<bits<6> mincode, string opasm> :
+  ArcUnaryInst<0b00101, mincode, opasm>;
 
 // Pattern generation for different instruction variants.
 multiclass MultiPat<SDPatternOperator InFrag,
@@ -280,6 +282,9 @@
 defm SEXB : ArcUnaryGEN4Inst<0b000101, "sexb">;
 defm SEXH : ArcUnaryGEN4Inst<0b000110, "sexh">;
 
+// Extension unary instruction definitions.
+defm FLS : ArcUnaryEXT5Inst<0b010011, "fls">;
+
 // General Unary Instruction fragments.
 def : Pat<(sext_inreg i32:$a, i8), (SEXB_rr i32:$a)>;
 def : Pat<(sext_inreg i32:$a, i16), (SEXH_rr i32:$a)>;


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