[PATCH] D106403: [RISCV] Avoid using x0,x0 vsetvli for vmv.x.s and vfmv.f.s unless we know the sew/lmul ratio is constant.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D106403#2895649 <https://reviews.llvm.org/D106403#2895649>, @rogfer01 wrote:

>> It would allow us to remove some code from the vsetvli insertion pass if these instructions weren't special.
>>
>> OTOH, it is perhaps confusing to provide vl for the intrinsic when the instruction doesn't need it. We'll need to rework isel patterns and may not be able to use ISD::EXTRACT_VECTOR_ELT directly for floating point.
>>
>> I think we need to weigh the options here. I'm leaning towards adding the VL to the intrinsics and instructions, but I might be persuaded to just keep this patch.
>
> I'm not super thrilled by requiring the addition of a `vl` if it is not used.
>
> If we add it, it may be documented as a no-op argument that the compiler can use as a hint for better code generation (in the context of other vector intrinsics using that same `vl`). It may be a bit of a tough sell though.

Ok I won't change the intrinsic. Any objection to this patch as is?


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https://reviews.llvm.org/D106403