[llvm] af8fa36 - [NFCI][TLI] prepare[US]REMEqFold(): don't add nonsensical 'exact' flag to rotates created

[Roman Lebedev via llvm-commits]

Author: Roman Lebedev
Date: 2021-07-22T23:02:58+03:00
New Revision: af8fa36bf0cf6a09d6f4d9ad16eab30bc2ec8719

URL: https://github.com/llvm/llvm-project/commit/af8fa36bf0cf6a09d6f4d9ad16eab30bc2ec8719
DIFF: https://github.com/llvm/llvm-project/commit/af8fa36bf0cf6a09d6f4d9ad16eab30bc2ec8719.diff

LOG: [NFCI][TLI] prepare[US]REMEqFold(): don't add nonsensical 'exact' flag to rotates created

As pointed out by Craig Topper.

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 71e90c3753b0a..79b347b92c470 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -5630,10 +5630,8 @@ TargetLowering::prepareUREMEqFold(EVT SETCCVT, SDValue REMNode,
     // We need ROTR to do this.
     if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ROTR, VT))
       return SDValue();
-    SDNodeFlags Flags;
-    Flags.setExact(true);
     // UREM: (rotr (mul N, P), K)
-    Op0 = DAG.getNode(ISD::ROTR, DL, VT, Op0, KVal, Flags);
+    Op0 = DAG.getNode(ISD::ROTR, DL, VT, Op0, KVal);
     Created.push_back(Op0.getNode());
   }
 
@@ -5897,10 +5895,8 @@ TargetLowering::prepareSREMEqFold(EVT SETCCVT, SDValue REMNode,
     // We need ROTR to do this.
     if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ROTR, VT))
       return SDValue();
-    SDNodeFlags Flags;
-    Flags.setExact(true);
     // SREM: (rotr (add (mul N, P), A), K)
-    Op0 = DAG.getNode(ISD::ROTR, DL, VT, Op0, KVal, Flags);
+    Op0 = DAG.getNode(ISD::ROTR, DL, VT, Op0, KVal);
     Created.push_back(Op0.getNode());
   }