[llvm] 1cda1e6 - [ARC] Add disassembly for the conditioned RSUB immediate instruction

[Mark Schimmel via llvm-commits]

Author: Thomas Johnson
Date: 2021-07-22T11:34:39-07:00
New Revision: 1cda1e618648d463f89eb5cea8c9849bc0074b24

URL: https://github.com/llvm/llvm-project/commit/1cda1e618648d463f89eb5cea8c9849bc0074b24
DIFF: https://github.com/llvm/llvm-project/commit/1cda1e618648d463f89eb5cea8c9849bc0074b24.diff

LOG: [ARC] Add disassembly for the conditioned RSUB immediate instruction

Differential Revision: https://reviews.llvm.org/D106497

Added: 
    

Modified: 
    llvm/lib/Target/ARC/ARCInstrFormats.td
    llvm/lib/Target/ARC/ARCInstrInfo.td
    llvm/test/MC/Disassembler/ARC/alu.txt
    llvm/test/MC/Disassembler/ARC/misc.txt

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/ARC/ARCInstrFormats.td b/llvm/lib/Target/ARC/ARCInstrFormats.td
index c95c71ff007bb..5f539c92c7452 100644
--- a/llvm/lib/Target/ARC/ARCInstrFormats.td
+++ b/llvm/lib/Target/ARC/ARCInstrFormats.td
@@ -262,7 +262,8 @@ class F32_SOP_RR<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
 }
 
 // Single Operand Immediate Instructions.
-// 1-register, unsigned 6-bit immediate Single Operand instruction.
+// 1-register, unsigned 6-bit immediate Single Operand instruction with
+// condition code.
 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
 // |B[2-0]  | 1| 1|            subop| F|B[5-3]  |U6           |1|cc       |
 class F32_SOP_CC_RU6<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
@@ -352,6 +353,30 @@ class F32_DOP_RU6<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
   let Inst{5-0} = A;
 }
 
+// 2-register, unsigned 6-bit immediate Dual Operand instruction with
+// condition code. This instruction uses B as the first 2 operands
+// (i.e, add.cc B, B, u6).
+// |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
+// |B[2-0]  | 1| 1|            subop| F|B[5-3]  |U6           |1|cc       |
+class F32_DOP_CC_RRU6<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
+                      string asmstr, list<dag> pattern> :
+  InstARC<4, outs, ins, asmstr, pattern> {
+  bits<5> cc;
+  bits<6> U6;
+  bits<6> B;
+  bits<6> A;
+
+  let Inst{31-27} = major;
+  let Inst{26-24} = B{2-0};
+  let Inst{23-22} = 0b11;
+  let Inst{21-16} = subop;
+  let Inst{15} = F;
+  let Inst{14-12} = B{5-3};
+  let Inst{11-6} = U6;
+  let Inst{5} = 1;
+  let Inst{4-0} = cc;
+}
+
 // 2-register, signed 12-bit immediate Dual Operand instruction.
 // This instruction uses B as the first 2 operands (i.e., add B, B, -128).
 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|

diff  --git a/llvm/lib/Target/ARC/ARCInstrInfo.td b/llvm/lib/Target/ARC/ARCInstrInfo.td
index 23e2d57b625ec..0813f5377a486 100644
--- a/llvm/lib/Target/ARC/ARCInstrInfo.td
+++ b/llvm/lib/Target/ARC/ARCInstrInfo.td
@@ -160,6 +160,23 @@ multiclass ArcBinaryInst<bits<5> major, bits<6> mincode,
                             []>
   { let Defs = [STATUS32]; }
 
+  def _cc_rru6 : F32_DOP_CC_RRU6<major, mincode, 0, (outs GPR32:$A),
+                                 (ins immU6:$U6, ccond:$cc, GPR32:$B),
+                                 !strconcat(opasm, ".$cc\t$A, $B, $U6"),
+                                 []> {
+                                   let Uses = [STATUS32];
+                                   let Constraints = "$A = $B";
+                                 }
+
+  def _cc_f_rru6 : F32_DOP_CC_RRU6<major, mincode, 1, (outs GPR32:$A),
+                                   (ins immU6:$U6, ccond:$cc, GPR32:$B),
+                                   !strconcat(opasm, ".$cc.f\t$A, $B, $U6"),
+                                   []> {
+                                     let Defs = [STATUS32];
+                                     let Uses = [STATUS32];
+                                     let Constraints = "$A = $B";
+                                   }
+
   // 2 register with 32-bit immediate variant.
   def _rrlimm : F32_DOP_RLIMM<major, mincode, 0,
                               (outs GPR32:$A),
@@ -243,6 +260,7 @@ defm SUB : ArcBinaryGEN4Inst<0b000010, "sub">;
 defm SUB1 : ArcBinaryGEN4Inst<0b010111, "sub1">;
 defm SUB2 : ArcBinaryGEN4Inst<0b011000, "sub2">;
 defm SUB3 : ArcBinaryGEN4Inst<0b011001, "sub3">;
+defm RSUB : ArcBinaryGEN4Inst<0b001110, "rsub">;
 defm OR  : ArcBinaryGEN4Inst<0b000101, "or",1>;
 defm AND : ArcBinaryGEN4Inst<0b000100, "and",1>;
 defm XOR : ArcBinaryGEN4Inst<0b000111, "xor",1>;

diff  --git a/llvm/test/MC/Disassembler/ARC/alu.txt b/llvm/test/MC/Disassembler/ARC/alu.txt
index 1068ac22ed85c..274233ed201bb 100644
--- a/llvm/test/MC/Disassembler/ARC/alu.txt
+++ b/llvm/test/MC/Disassembler/ARC/alu.txt
@@ -104,3 +104,12 @@
 
 # CHECK: sub3.f %fp, %fp, -1
 0x99 0x23 0xff 0xbf
+
+# CHECK: rsub.eq %r0, %r0, 30
+0xce 0x20 0xa1 0x07
+
+# CHECK: rsub.ne %r0, %r0, 31
+0xce 0x20 0xe2 0x07
+
+# CHECK: rsub.ne.f %r0, %r0, 31
+0xce 0x20 0xe2 0x87

diff  --git a/llvm/test/MC/Disassembler/ARC/misc.txt b/llvm/test/MC/Disassembler/ARC/misc.txt
index 04fdfd7ca877a..16e5f090baca8 100644
--- a/llvm/test/MC/Disassembler/ARC/misc.txt
+++ b/llvm/test/MC/Disassembler/ARC/misc.txt
@@ -16,6 +16,12 @@
 # CHECK: mov %r1, 20
 0x4a 0x21 0x00 0x05
 
+# CHECK: mov.eq %r0, 32
+0xca 0x20 0x21 0x08
+
+# CHECK: mov.ne %r0, 0
+0xca 0x20 0x22 0x00
+
 # CHECK: st.aw %fp, [%sp,-4]
 0xfc 0x1c 0xc8 0xb6