[PATCH] D106549: [AArch64][SVE] Combine bitcasts to predicate types with vector inserts of loads

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


================
Comment at: llvm/lib/Target/AArch64/SVEIntrinsicOpts.cpp:294
+      continue;
+    unsigned MinSVEVectorSize = ST.getMinSVEVectorSizeInBits() / 128;
+    if (MinSVEVectorSize == 0)
----------------
Do you need to check getMaxSVEVectorSizeInBits() somewhere?

This code could probably use some comments explaining why it's checking various conditions.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106549/new/

https://reviews.llvm.org/D106549