[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.
Jianjian Guan via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 21 23:53:06 PDT 2021
jacquesguan added inline comments.
================
Comment at: clang/include/clang/Basic/riscv_vector.td:693
+ let Name = op # eew64 # "_v", IRName = op, IRNameMask = op # "_mask",
+ RequiredExtensions = ["Xlen64"] in {
+ def: RVVBuiltin<"v", "vPCe" # eew64_type # "Uv", type>;
----------------
jrtc27 wrote:
> Xlen64 is not an extension. Nor is RV64I, even, it is a base ISA, but that would at least be somewhat defensible. In fact, Xlen64 would be parsed as a valid non-standard extension called "Xlen" with major version 64 and minor version 0, just like any other Xfoo.
So change Xlen64 to RV64 or create a new field of RVVBuiltin to describle it? Which one do you think is better?
Repository:
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CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D106518/new/
https://reviews.llvm.org/D106518
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