[llvm] 8d86562 - [RegisterCoalescer] Make resolveConflicts aware of earlyclobber

[ShihPo Hung via llvm-commits]

Author: ShihPo Hung
Date: 2021-07-22T12:11:10+08:00
New Revision: 8d86562e5f1f0bddb0a1e35c46577046530adadb

URL: https://github.com/llvm/llvm-project/commit/8d86562e5f1f0bddb0a1e35c46577046530adadb
DIFF: https://github.com/llvm/llvm-project/commit/8d86562e5f1f0bddb0a1e35c46577046530adadb.diff

LOG: [RegisterCoalescer] Make resolveConflicts aware of earlyclobber

Prior to this patch, it skipped the instruction defining VNI when checking if the tainted lanes are used.
In the given example, VRGATHER is an illegal instruction because its DstReg overlaps with SrcReg.

Therefore we need to check the defining instruction as well when there is an earlyclobber constraint.

Reviewed By: qcolombet

Differential Revision: https://reviews.llvm.org/D105684

Added: 
    

Modified: 
    llvm/lib/CodeGen/RegisterCoalescer.cpp
    llvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
index 7daa677937544..751f79e66b731 100644
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -3071,8 +3071,10 @@ bool JoinVals::resolveConflicts(JoinVals &Other) {
     MachineBasicBlock::iterator MI = MBB->begin();
     if (!VNI->isPHIDef()) {
       MI = Indexes->getInstructionFromIndex(VNI->def);
-      // No need to check the instruction defining VNI for reads.
-      ++MI;
+      if (!VNI->def.isEarlyClobber()) {
+        // No need to check the instruction defining VNI for reads.
+        ++MI;
+      }
     }
     assert(!SlotIndex::isSameInstr(VNI->def, TaintExtent.front().first) &&
            "Interference ends on VNI->def. Should have been handled earlier");

diff  --git a/llvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir b/llvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir
index 6b19f65c6c79e..8db36981fd5a1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir
@@ -9,10 +9,11 @@ body:             |
     liveins: $x10
     ; CHECK-LABEL: name: test_earlyclobber
     ; CHECK: liveins: $x10
-    ; CHECK: undef %2.sub_vrm2_0:vrn2m2 = PseudoVLE32_V_M2 $x10, 1, 5
-    ; CHECK: %2.sub_vrm2_1:vrn2m2 = PseudoVLE32_V_M2 $x10, 1, 5
+    ; CHECK: undef %0.sub_vrm2_0:vrn2m2 = PseudoVLE32_V_M2 $x10, 1, 5
+    ; CHECK: %0.sub_vrm2_1:vrn2m2 = PseudoVLE32_V_M2 $x10, 1, 5
     ; CHECK: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 $x10, 1, 5
-    ; CHECK: early-clobber %2.sub_vrm2_0:vrn2m2 = PseudoVRGATHER_VI_M2 %2.sub_vrm2_0, 0, 1, 5, implicit $vl, implicit $vtype
+    ; CHECK: undef early-clobber %2.sub_vrm2_0:vrn2m2 = PseudoVRGATHER_VI_M2 %0.sub_vrm2_0, 0, 1, 5, implicit $vl, implicit $vtype
+    ; CHECK: %2.sub_vrm2_1:vrn2m2 = COPY %0.sub_vrm2_1
     ; CHECK: PseudoVSUXSEG2EI32_V_M2_M2 %2, $x10, [[PseudoVLE32_V_M2_]], 1, 5, implicit $vl, implicit $vtype
     undef %0.sub_vrm2_0:vrn2m2 = PseudoVLE32_V_M2 $x10, 1, 5
     %0.sub_vrm2_1:vrn2m2 = PseudoVLE32_V_M2 $x10, 1, 5