[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan created this revision.
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Disable EEW=64 for vector index load/store when XLEN=32.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D106518

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/test/CodeGen/RISCV/rvv/invalid-eew.ll
  llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsoxei-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsuxei-rv32.ll
  llvm/test/MC/RISCV/rvv/invalid-eew.s

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