[PATCH] D106471: [DAGCombiner][RISCV][AMDGPU] Call SimplifyDemandedBits at the end of visitMULHU to enable known bits contant folding.

[Carl Ritson via Phabricator via llvm-commits]

critson added inline comments.


================
Comment at: llvm/test/CodeGen/AMDGPU/sdiv64.ll:1425
-; GCN-NEXT:    v_mul_hi_u32 v6, 24, v4
-; GCN-NEXT:    v_mul_hi_u32 v4, 0, v4
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
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critson wrote:
> RKSimon wrote:
> > craig.topper wrote:
> > > This also points to a failure to canonicalize constants to the RHS so the isNullValue check in visitMULHU would work. I tried to add the canonicalization without this patch, but ended up with a verifier failure on some AMDGPU tests.
> > > 
> > > It appears the simplification introduced in this patch catches something even earlier and produces simpler code that doesn't hit the verifier error.
> > @foad @arsenm - any ideas?
> > ```
> > *** Bad machine code: VOP* instruction violates constant bus restriction ***
> > - function:    v_test_sdiv_k_num_i64
> > - basic block: %bb.0  (0x238f3f455f0)
> > - instruction: %160:vgpr_32 = V_ADDC_U32_e32 %70:sreg_32, %161:vgpr_32, implicit-def dead $vcc, implicit $vcc, implicit $exec
> > ```
> There appears to be a verifier bug, where VCC is being counted toward constant bus usage for V_ADDC (where it is implicit).
> The instruction is legal.
Please ignore me - I misread the documentation.
The verifier is correct.


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https://reviews.llvm.org/D106471