[llvm] 4de74a7 - [MachineVerifier] Make INSERT_SUBREG diagnostic respect operand 2 subregs

[Jon Roelofs via llvm-commits]

Author: Jon Roelofs
Date: 2021-07-21T08:47:17-07:00
New Revision: 4de74a7c4da3516d0d9119452cc073b061716b5d

URL: https://github.com/llvm/llvm-project/commit/4de74a7c4da3516d0d9119452cc073b061716b5d
DIFF: https://github.com/llvm/llvm-project/commit/4de74a7c4da3516d0d9119452cc073b061716b5d.diff

LOG: [MachineVerifier] Make INSERT_SUBREG diagnostic respect operand 2 subregs

This came out of post-commit review: https://reviews.llvm.org/D105953#inline-1012919

Thanks uabelho!

Added: 
    

Modified: 
    llvm/lib/CodeGen/MachineVerifier.cpp
    llvm/test/MachineVerifier/test_insert_subreg.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index dde0a24d90ac..7e3198af02cd 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1783,8 +1783,11 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
     // TODO: verify we have properly encoded deopt arguments
   } break;
   case TargetOpcode::INSERT_SUBREG: {
-    unsigned InsertedSize =
-        TRI->getRegSizeInBits(MI->getOperand(2).getReg(), *MRI);
+    unsigned InsertedSize;
+    if (unsigned SubIdx = MI->getOperand(2).getSubReg())
+      InsertedSize = TRI->getSubRegIdxSize(SubIdx);
+    else
+      InsertedSize = TRI->getRegSizeInBits(MI->getOperand(2).getReg(), *MRI);
     unsigned SubRegSize = TRI->getSubRegIdxSize(MI->getOperand(3).getImm());
     if (SubRegSize < InsertedSize) {
       report("INSERT_SUBREG expected inserted value to have equal or lesser "

diff  --git a/llvm/test/MachineVerifier/test_insert_subreg.mir b/llvm/test/MachineVerifier/test_insert_subreg.mir
index f68c29edd3f1..593786c73dd4 100644
--- a/llvm/test/MachineVerifier/test_insert_subreg.mir
+++ b/llvm/test/MachineVerifier/test_insert_subreg.mir
@@ -10,7 +10,7 @@ tracksRegLiveness: true
 liveins:
 body:             |
   bb.0:
-    liveins: $s0, $h1
+    liveins: $s0, $h1, $q2
 
     %0:fpr32 = COPY $s0
 
@@ -28,4 +28,9 @@ body:             |
     %7:fpr128 = IMPLICIT_DEF
     %8:fpr128 = INSERT_SUBREG %7:fpr128, %0:fpr32, %subreg.ssub
 
+    ; CHECK-NOT: *** Bad machine code:
+    %9:fpr128 = COPY $q2
+    %10:fpr128 = IMPLICIT_DEF
+    %11:fpr128 = INSERT_SUBREG %10:fpr128, %9.ssub, %subreg.ssub
+
 ...