[PATCH] D105575: [AArch64][SME] Add zero instruction

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes updated this revision to Diff 360471.
c-rhodes set the repository for this revision to rG LLVM Github Monorepo.
c-rhodes added a comment.

- Address comments.
- Replaced MatrixTileList<EltSize> operands with a single operand. Since legal tiles (8/16/32) get mapped to 64-bit tiles then register mask, and the shortest possible tile lists are defined via aliases, individual operands for each elt size isn't necessary and adds complication.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105575/new/

https://reviews.llvm.org/D105575

Files:
  llvm/lib/Target/AArch64/AArch64RegisterInfo.td
  llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
  llvm/lib/Target/AArch64/SMEInstrFormats.td
  llvm/test/MC/AArch64/SME/zero-diagnostics.s
  llvm/test/MC/AArch64/SME/zero.s

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