[PATCH] D106447: [DAGCombine] DAGTypeLegalizer::GenWidenVectorLoads(): make use of dereferenceability knowledge

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:5277
 
+  if (LdAlign && !WidenWidth.isScalable() && LdAlign < WidenWidth / 8 &&
+      LD->getPointerInfo().isDereferenceable(WidenWidth / 8, *DAG.getContext(),
----------------
pengfei wrote:
> Is this a trick that turning unaligned memory to aligned if the widen bits are dereferenceable?
> The problem I can think is we may mistakenly generate `movaps` on an unaligned address which will crush in runtime.
> Did I misunderstand something here? Because I saw the tests are using `movups` in fact.
Note that `LdAlign` is *not* used as the alignment for the new load.
It's confusingly named as such, and is only used by `FindMemType`
as a measure of how many bytes are known-dereferenceable.

Hopefully this is better.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106447/new/

https://reviews.llvm.org/D106447