[PATCH] D106447: [DAGCombine] DAGTypeLegalizer::GenWidenVectorLoads(): make use of dereferenceability knowledge

[Pengfei Wang via Phabricator via llvm-commits]

pengfei added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:5277
 
+  if (LdAlign && !WidenWidth.isScalable() && LdAlign < WidenWidth / 8 &&
+      LD->getPointerInfo().isDereferenceable(WidenWidth / 8, *DAG.getContext(),
----------------
Is this a trick that turning unaligned memory to aligned if the widen bits are dereferenceable?
The problem I can think is we may mistakenly generate `movaps` on an unaligned address which will crush in runtime.
Did I misunderstand something here? Because I saw the tests are using `movups` in fact.


Repository:
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  https://reviews.llvm.org/D106447/new/

https://reviews.llvm.org/D106447