[PATCH] D106399: [VectorCombine] Widening of partial vector loads

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri updated this revision to Diff 360412.
lebedev.ri added a comment.

In D106399#2892863 <https://reviews.llvm.org/D106399#2892863>, @RKSimon wrote:

> Thanks for looking at this - I'd delayed requesting something like this until we have a better idea of what the non-pow2 SLP IR from D57059 <https://reviews.llvm.org/D57059> is likely to look like.

Even if SLP learns to emit wide-enough loads (which it should, regardless of non-pow2 vectorization support/etc),
i would guess we'd still want this, because here in IR we have much more information to deduce
the legality of such a transformation rather than leaving it up to the backend.

> I also ended up wondering whether we should consider using the dereferencable data in DAGTypeLegalizer::GenWidenVectorLoads? As that would help with the float3 case on D106280 <https://reviews.llvm.org/D106280> that raised concern

I actually tried looking at exactly that before doing this, without much success.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106399/new/

https://reviews.llvm.org/D106399

Files:
  llvm/include/llvm/Analysis/TargetTransformInfo.h
  llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
  llvm/include/llvm/CodeGen/BasicTTIImpl.h
  llvm/lib/Analysis/TargetTransformInfo.cpp
  llvm/lib/Transforms/Vectorize/VectorCombine.cpp
  llvm/test/Transforms/VectorCombine/X86/load-inseltpoison.ll
  llvm/test/Transforms/VectorCombine/X86/load-widening.ll
  llvm/test/Transforms/VectorCombine/X86/load.ll

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