[PATCH] D106286: [RISCV] Add a test showing an incorrect vsetvli insertion

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck marked an inline comment as done.
frasercrmck added a comment.

In D106286#2890831 <https://reviews.llvm.org/D106286#2890831>, @craig.topper wrote:

> That's very interesting and I think it has always been broken. [...[
> We don't have a VL to use here and I don't think we should make one up. I think the right fix is to add the VL argument to the intrinsic and the instruction.

Interesting, thanks for the context. I'll keep discussion about the fix(es) to D106403 <https://reviews.llvm.org/D106403> to keep everything well-threaded.



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Comment at: llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 | FileCheck %s
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craig.topper wrote:
> Can we use 
> 
> ```
> define i32 @foo(<vscale x 2 x i32> %a, <vscale x 4 x i64> %x, <vscale x 4 x i64>* %y) {
>   %index = add <vscale x 4 x i64> %x, %x
>   store <vscale x 4 x i64> %index, <vscale x 4 x i64>* %y
>   %elt = extractelement <vscale x 2 x i32> %a, i64 0
>   ret i32 %elt
> }
> ```
> 
> to avoid the mix of fixed and scalable.
Sure. The original test was a mix but I think it's best to keep it as simple as possible.


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https://reviews.llvm.org/D106286