[PATCH] D106286: [RISCV] Add a test showing an incorrect vsetvli insertion

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 | FileCheck %s
----------------
Can we use 

```
define i32 @foo(<vscale x 2 x i32> %a, <vscale x 4 x i64> %x, <vscale x 4 x i64>* %y) {
  %index = add <vscale x 4 x i64> %x, %x
  store <vscale x 4 x i64> %index, <vscale x 4 x i64>* %y
  %elt = extractelement <vscale x 2 x i32> %a, i64 0
  ret i32 %elt
}
```

to avoid the mix of fixed and scalable.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106286/new/

https://reviews.llvm.org/D106286