[PATCH] D105575: [AArch64][SME] Add zero instruction

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes added inline comments.


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Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:661
+class sme_zero_inst<string mnemonic>
+    : I<(outs MatrixTileList64:$imm), (ins),
+        mnemonic, "\t$imm", "", []>, Sched<[]> {
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bryanpkc wrote:
> c-rhodes wrote:
> > bryanpkc wrote:
> > > Wouldn't it be better for the instruction to accept an output `RegisterOperand` that covers all possible tile types, which would allow register allocation to assign the appropriate tile registers? Doing so would also allow us to distinguish between `zero { za0.d, za4.d }` and `zero { za0.s }` when we need to parse assembly code back into machine IR with correct register semantics.
> > > Wouldn't it be better for the instruction to accept an output `RegisterOperand` that covers all possible tile types, which would allow register allocation to assign the appropriate tile registers? Doing so would also allow us to distinguish between `zero { za0.d, za4.d }` and `zero { za0.s }` when we need to parse assembly code back into machine IR with correct register semantics.
> > 
> > I've not given that a great deal of thought yet to be honest, our focus is on MC layer support at the moment, may revisit this in the future.
> We also went with an immediate operand at first, but eventually replaced it with a register operand, mainly to allow register allocation to work.
> We also went with an immediate operand at first, but eventually replaced it with a register operand, mainly to allow register allocation to work.

Your approach sounds more complete, I'd be interested in taking a look, are you able to upstream it?


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  https://reviews.llvm.org/D105575/new/

https://reviews.llvm.org/D105575