[PATCH] D106230: [RISCV] Add custom isel to select (and (srl X, C1), C2) and (and (shl X, C1), C2)

Luís Marques via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Jul 20 06:36:27 PDT 2021

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luismarques accepted this revision.
luismarques added a comment.
This revision is now accepted and ready to land.

LGTM. Some nice wins!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106230/new/

https://reviews.llvm.org/D106230

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