[PATCH] D106353: [PowerPC] use lfiwax/lfiwzx for scalar_to_vector + load at PWR7

[ChenZheng via Phabricator via llvm-commits]

shchenz created this revision.
shchenz added reviewers: nemanjai, jsji, qiucf, PowerPC.
Herald added subscribers: steven.zhang, kbarton, hiraditya.
shchenz requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

We handle well for `scalar_to_vector + load` for PWR8 and above. This means using `lfiwax/lfiwzx` for above pattern thus we don't need the memory to do the type change.

This patch adds a similar code-gen improvement for PWR7.

We still miss handling the case for i32->i64 sign-ext and unsigned-ext. PowerPC backend fails to recognize `build_vector t1, t1` as `scalar_to_vector + vector_shuffle<0, 0>`.  So it will not be hit by this patch. We will handle this in a later patch.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D106353

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/load-and-splat.ll

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