[PATCH] D106318: [POC][RISCV] Take into account instruction compressibility in materialization cost

[Luís Marques via Phabricator via llvm-commits]

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This patch is currently only meant to illustrate a possible approach to address a constant materialization regression in D105417 <https://reviews.llvm.org/D105417>, etc. It takes the D105417 <https://reviews.llvm.org/D105417> patch and adds the `getInstSeqCost` function I was using in an old (unpublished) constant materialization patch.

Notes:

- To better illustrate the original implementation, I kept the boolean `HasRVC` and `OptSize` parameters in `getInstSeqCost`. But they aren't actually being used in this patch. The tests generally don't have the C extension, so without additional test changes you wouldn't see any difference. Keeping those changes out of this patch makes the differences more obvious, IMO. Plugging the size optimization flag is also not quite trivial, and would further obscure the test differences.

- I also used `getInstSeqCost` in the `generateInstSeqImpl` tentative optimizations, to illustrate how I was originally using this function. To address the `isDesirableToCommuteWithShift`-related regression it only needs to be used in `getIntMatCost`, though.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D106318

Files:
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
  llvm/test/CodeGen/RISCV/add-before-shl.ll
  llvm/test/CodeGen/RISCV/atomic-rmw.ll
  llvm/test/CodeGen/RISCV/atomic-signext.ll
  llvm/test/CodeGen/RISCV/div.ll
  llvm/test/CodeGen/RISCV/rv64zba.ll
  llvm/test/CodeGen/RISCV/rv64zbp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
  llvm/test/CodeGen/RISCV/vararg.ll

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