[llvm] 6c0e689 - [SystemZ] Handle NoRegister in SystemZTargetLowering::emitMemMemWrapper().

[Jonas Paulsson via llvm-commits]

Author: Jonas Paulsson
Date: 2021-07-19T20:04:44+02:00
New Revision: 6c0e6895d014096ad7375e95997575ad1e8da020

URL: https://github.com/llvm/llvm-project/commit/6c0e6895d014096ad7375e95997575ad1e8da020
DIFF: https://github.com/llvm/llvm-project/commit/6c0e6895d014096ad7375e95997575ad1e8da020.diff

LOG: [SystemZ]  Handle NoRegister in SystemZTargetLowering::emitMemMemWrapper().

Bugfix: The compiler should be able to generate a memset to nullptr.

Review: Ulrich Weigand

Added: 
    

Modified: 
    llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
    llvm/test/CodeGen/SystemZ/memset-05.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index 6b6fdcaf5630b..d70d48638b140 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -7809,6 +7809,17 @@ MachineBasicBlock *SystemZTargetLowering::emitMemMemWrapper(
   // Check for the loop form, in which operand 5 is the trip count.
   if (MI.getNumExplicitOperands() > 5) {
     Register StartCountReg = MI.getOperand(5).getReg();
+    bool HaveSingleBase = DestBase.isIdenticalTo(SrcBase);
+
+    auto loadZeroAddress = [&]() -> MachineOperand {
+      Register Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
+      BuildMI(*MBB, MI, DL, TII->get(SystemZ::LGHI), Reg).addImm(0);
+      return MachineOperand::CreateReg(Reg, false);
+    };
+    if (DestBase.isReg() && DestBase.getReg() == SystemZ::NoRegister)
+      DestBase = loadZeroAddress();
+    if (SrcBase.isReg() && SrcBase.getReg() == SystemZ::NoRegister)
+      SrcBase = HaveSingleBase ? DestBase : loadZeroAddress();
 
     MachineBasicBlock *StartMBB = nullptr;
     MachineBasicBlock *LoopMBB = nullptr;
@@ -7816,7 +7827,6 @@ MachineBasicBlock *SystemZTargetLowering::emitMemMemWrapper(
     MachineBasicBlock *DoneMBB = nullptr;
     MachineBasicBlock *AllDoneMBB = nullptr;
 
-    bool HaveSingleBase = DestBase.isIdenticalTo(SrcBase);
     Register StartSrcReg = forceReg(MI, SrcBase, TII);
     Register StartDestReg =
         (HaveSingleBase ? StartSrcReg : forceReg(MI, DestBase, TII));

diff  --git a/llvm/test/CodeGen/SystemZ/memset-05.ll b/llvm/test/CodeGen/SystemZ/memset-05.ll
index 780d107d7e594..5754660705631 100644
--- a/llvm/test/CodeGen/SystemZ/memset-05.ll
+++ b/llvm/test/CodeGen/SystemZ/memset-05.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; Test memset 0 with variable length
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@@ -92,7 +93,30 @@ define void @fun2(i8* %Addr, i32 %Len) {
   ret void
 }
 
-; CHECK:       .Ltmp0:
+; Test that a memset to nullptr compiles.
+define void @fun3(i64 %Len) {
+; CHECK-LABEL: fun3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    aghi %r2, -1
+; CHECK-NEXT:    cgibe %r2, -1, 0(%r14)
+; CHECK-NEXT:  .LBB3_1:
+; CHECK-NEXT:    srlg %r0, %r2, 8
+; CHECK-NEXT:    lghi %r1, 0
+; CHECK-NEXT:    cgije %r0, 0, .LBB3_3
+; CHECK-NEXT:  .LBB3_2: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    xc 0(256,%r1), 0(%r1)
+; CHECK-NEXT:    la %r1, 256(%r1)
+; CHECK-NEXT:    brctg %r0, .LBB3_2
+; CHECK-NEXT:  .LBB3_3:
+; CHECK-NEXT:    exrl %r2, .Ltmp2
+; CHECK-NEXT:    br %r14
+  call void @llvm.memset.p0i8.i64(i8* null, i8 0, i64 %Len, i1 false)
+  ret void
+}
+
+; CHECK:       .Ltmp2:
+; CHECK-NEXT: 	 xc 0(1,%r1), 0(%r1)
+; CHECK-NEXT:  .Ltmp0:
 ; CHECK-NEXT:    xc 0(1,%r2), 0(%r2)
 ; CHECK-NEXT:  .Ltmp1:
 ; CHECK-NEXT:    xc 0(1,%r3), 0(%r3)