[PATCH] D105575: [AArch64][SME] Add zero instruction

[David Sherwood via Phabricator via llvm-commits]

david-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp:3806
+
+    unsigned RegNum = matchMatrixTileRegName(Name);
+    if (!RegNum)
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Is 'RegNum' guaranteed to always be > 0 for a valid register?


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Comment at: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp:3811
+    StringRef Tail = Name.drop_front(DotPosition);
+    const auto &KindRes = parseVectorKind(Tail, RegKind::Matrix);
+    ElementWidth = KindRes->second;
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To be honest it's quite hard to review this because I don't know what parseVectorKind returns. Can we specify the type instead of 'auto'?


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Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:688
+  def : InstAlias<"zero\t\\{za1.s,za2.s\\}", (!cast<Instruction>(NAME) 0b01100110), 1>;
+  def : InstAlias<"zero\t\\{za2.s,za3.s\\}", (!cast<Instruction>(NAME) 0b11001100), 1>;
+  def : InstAlias<"zero\t\\{za0.s,za1.s,za2.s\\}", (!cast<Instruction>(NAME) 0b01110111), 1>;
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Are we missing ones for {za1.s,za3.s} and {z0.s,za2.s}?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105575/new/

https://reviews.llvm.org/D105575