[PATCH] D106264: [SLP]Fix possible crash on unreachable incoming values sorting.
Alexey Bataev via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 19 04:55:46 PDT 2021
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGd8d8b4574ab4: [SLP]Fix possible crash on unreachable incoming values sorting. (authored by ABataev).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D106264/new/
https://reviews.llvm.org/D106264
Files:
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
llvm/test/Transforms/SLPVectorizer/X86/unreachable.ll
Index: llvm/test/Transforms/SLPVectorizer/X86/unreachable.ll
===================================================================
--- llvm/test/Transforms/SLPVectorizer/X86/unreachable.ll
+++ llvm/test/Transforms/SLPVectorizer/X86/unreachable.ll
@@ -62,3 +62,29 @@
ret void
}
+define void @bar() {
+; CHECK-LABEL: @bar(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP:%.*]] = load atomic i8*, i8** undef unordered, align 8
+; CHECK-NEXT: br label [[BB6:%.*]]
+; CHECK: bb5:
+; CHECK-NEXT: [[TMP4:%.*]] = load atomic i8*, i8** undef unordered, align 8
+; CHECK-NEXT: br label [[BB6]]
+; CHECK: bb6:
+; CHECK-NEXT: [[TMP7:%.*]] = phi i8* [ [[TMP]], [[BB5:%.*]] ], [ undef, [[BB:%.*]] ]
+; CHECK-NEXT: [[TMP8:%.*]] = phi i8* [ [[TMP4]], [[BB5]] ], [ undef, [[BB]] ]
+; CHECK-NEXT: ret void
+;
+bb:
+ %tmp = load atomic i8*, i8** undef unordered, align 8
+ br label %bb6
+
+bb5: ; No predecessors!
+ %tmp4 = load atomic i8*, i8** undef unordered, align 8
+ br label %bb6
+
+bb6: ; preds = %bb5, %bb
+ %tmp7 = phi i8* [ %tmp, %bb5 ], [ undef, %bb ]
+ %tmp8 = phi i8* [ %tmp4, %bb5 ], [ undef, %bb ]
+ ret void
+}
Index: llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
===================================================================
--- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -8440,8 +8440,10 @@
if (auto *I2 = dyn_cast<Instruction>(Opcodes2[I])) {
DomTreeNodeBase<BasicBlock> *NodeI1 = DT->getNode(I1->getParent());
DomTreeNodeBase<BasicBlock> *NodeI2 = DT->getNode(I2->getParent());
- assert(NodeI1 && "Should only process reachable instructions");
- assert(NodeI2 && "Should only process reachable instructions");
+ if (!NodeI1)
+ return NodeI2 != nullptr;
+ if (!NodeI2)
+ return false;
assert((NodeI1 == NodeI2) ==
(NodeI1->getDFSNumIn() == NodeI2->getDFSNumIn()) &&
"Different nodes should have different DFS numbers");
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