[PATCH] D106261: [ARM][LowOverheadLoops] Allow unpredicated VORRs if the operand def produces zeroed false lanes

[Sam Tebbs via Phabricator via llvm-commits]

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  A VORR of the form $qX = VORR $qY, $qY essentially just moves $qY into
  $qX but is currently not allowed in a tail-predicated loop.
  
  If the definition of $qY produces zeroed false lanes then we now
  consider the VORR to produce zeroed false lanes as well, since it
  doesn't modify the incoming lane values.
  
  This required modifying some existing tests that used a VORR of this
  format to test unpredicated instructions that defined a live-out.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D106261

Files:
  llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-add-operand-liveout.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp16-reduce.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vorr-false-lanes-zero.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/wlstp.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-liveout-lsr-shift.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-opcode-liveout.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-operand-liveout.mir

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