[PATCH] D105836: [AMDGPU] Add TII::isAmbientPhysRegUse() to allow VOP rematerialization

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D105836#2877797 <https://reviews.llvm.org/D105836#2877797>, @kparzysz wrote:

> In D105836#2877775 <https://reviews.llvm.org/D105836#2877775>, @arsenm wrote:
>
>> We specifically do not want anything trying to manage the value of the register here. It's a predicate register and we want the value to be whatever it happens to be at that point. If the predicate was on for a lane at the def, it's fine if that bit is off at the use. The inverse would be an invalid situation to begin with
>
> So you don't care if `exec` has a different value at `OldIdx` and `UseIdx`?

Yes. It's a bitmask of active lanes. It's safe to rematerialize the instruction for lanes which are active at the def, but only a subset are at the use which would look like a different register value


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105836/new/

https://reviews.llvm.org/D105836