[PATCH] D106230: [RISCV] Add custom isel to select (and (srl X, C1), C2) and (and (shl X, C1), C2)

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 359664.
craig.topper added a comment.

Add another special case (and (srl (sexti32 Y), c2), c1) -> (srliw (sraiw Y, 31), c2-31). This occurs in sdiv/srem by constant power of 2.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106230/new/

https://reviews.llvm.org/D106230

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/CodeGen/RISCV/div.ll
  llvm/test/CodeGen/RISCV/rem.ll
  llvm/test/CodeGen/RISCV/rv32zbp.ll
  llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
  llvm/test/CodeGen/RISCV/rv64zbp.ll
  llvm/test/CodeGen/RISCV/srem-lkk.ll

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