[llvm] 00c1cc8 - [RISCV] Add more i32 srem/sdiv with power of 2 constant tests. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2021-07-18T00:21:14-07:00
New Revision: 00c1cc867fbccf46166de0b9f6975f31c59ee540

URL: https://github.com/llvm/llvm-project/commit/00c1cc867fbccf46166de0b9f6975f31c59ee540
DIFF: https://github.com/llvm/llvm-project/commit/00c1cc867fbccf46166de0b9f6975f31c59ee540.diff

LOG: [RISCV] Add more i32 srem/sdiv with power of 2 constant tests. NFC

Add a small power 2 srem test to match existing sdiv test. Add
larger power of 2 test to both.

The larger constant test shows materialization of a constant
for an AND in the RV64 code. We should be using W shift instructions
to match the RV32 code.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/div.ll
    llvm/test/CodeGen/RISCV/rem.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/div.ll b/llvm/test/CodeGen/RISCV/div.ll
index 279329dd277d..dd9e6fa1cc90 100644
--- a/llvm/test/CodeGen/RISCV/div.ll
+++ b/llvm/test/CodeGen/RISCV/div.ll
@@ -730,6 +730,48 @@ define i32 @sdiv_pow2(i32 %a) nounwind {
   ret i32 %1
 }
 
+define i32 @sdiv_pow2_2(i32 %a) nounwind {
+; RV32I-LABEL: sdiv_pow2_2:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    srai a1, a0, 31
+; RV32I-NEXT:    srli a1, a1, 16
+; RV32I-NEXT:    add a0, a0, a1
+; RV32I-NEXT:    srai a0, a0, 16
+; RV32I-NEXT:    ret
+;
+; RV32IM-LABEL: sdiv_pow2_2:
+; RV32IM:       # %bb.0:
+; RV32IM-NEXT:    srai a1, a0, 31
+; RV32IM-NEXT:    srli a1, a1, 16
+; RV32IM-NEXT:    add a0, a0, a1
+; RV32IM-NEXT:    srai a0, a0, 16
+; RV32IM-NEXT:    ret
+;
+; RV64I-LABEL: sdiv_pow2_2:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    sext.w a1, a0
+; RV64I-NEXT:    srli a1, a1, 47
+; RV64I-NEXT:    lui a2, 16
+; RV64I-NEXT:    addiw a2, a2, -1
+; RV64I-NEXT:    and a1, a1, a2
+; RV64I-NEXT:    add a0, a0, a1
+; RV64I-NEXT:    sraiw a0, a0, 16
+; RV64I-NEXT:    ret
+;
+; RV64IM-LABEL: sdiv_pow2_2:
+; RV64IM:       # %bb.0:
+; RV64IM-NEXT:    sext.w a1, a0
+; RV64IM-NEXT:    srli a1, a1, 47
+; RV64IM-NEXT:    lui a2, 16
+; RV64IM-NEXT:    addiw a2, a2, -1
+; RV64IM-NEXT:    and a1, a1, a2
+; RV64IM-NEXT:    add a0, a0, a1
+; RV64IM-NEXT:    sraiw a0, a0, 16
+; RV64IM-NEXT:    ret
+  %1 = sdiv i32 %a, 65536
+  ret i32 %1
+}
+
 define i32 @sdiv_constant_lhs(i32 %a) nounwind {
 ; RV32I-LABEL: sdiv_constant_lhs:
 ; RV32I:       # %bb.0:

diff  --git a/llvm/test/CodeGen/RISCV/rem.ll b/llvm/test/CodeGen/RISCV/rem.ll
index dea41e1d727d..8712f532d5ae 100644
--- a/llvm/test/CodeGen/RISCV/rem.ll
+++ b/llvm/test/CodeGen/RISCV/rem.ll
@@ -117,6 +117,98 @@ define i32 @srem(i32 %a, i32 %b) nounwind {
   ret i32 %1
 }
 
+define i32 @srem_pow2(i32 %a) nounwind {
+; RV32I-LABEL: srem_pow2:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    srai a1, a0, 31
+; RV32I-NEXT:    srli a1, a1, 29
+; RV32I-NEXT:    add a1, a0, a1
+; RV32I-NEXT:    andi a1, a1, -8
+; RV32I-NEXT:    sub a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32IM-LABEL: srem_pow2:
+; RV32IM:       # %bb.0:
+; RV32IM-NEXT:    srai a1, a0, 31
+; RV32IM-NEXT:    srli a1, a1, 29
+; RV32IM-NEXT:    add a1, a0, a1
+; RV32IM-NEXT:    andi a1, a1, -8
+; RV32IM-NEXT:    sub a0, a0, a1
+; RV32IM-NEXT:    ret
+;
+; RV64I-LABEL: srem_pow2:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    sext.w a1, a0
+; RV64I-NEXT:    srli a1, a1, 60
+; RV64I-NEXT:    andi a1, a1, 7
+; RV64I-NEXT:    add a1, a0, a1
+; RV64I-NEXT:    andi a1, a1, -8
+; RV64I-NEXT:    subw a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64IM-LABEL: srem_pow2:
+; RV64IM:       # %bb.0:
+; RV64IM-NEXT:    sext.w a1, a0
+; RV64IM-NEXT:    srli a1, a1, 60
+; RV64IM-NEXT:    andi a1, a1, 7
+; RV64IM-NEXT:    add a1, a0, a1
+; RV64IM-NEXT:    andi a1, a1, -8
+; RV64IM-NEXT:    subw a0, a0, a1
+; RV64IM-NEXT:    ret
+  %1 = srem i32 %a, 8
+  ret i32 %1
+}
+
+define i32 @srem_pow2_2(i32 %a) nounwind {
+; RV32I-LABEL: srem_pow2_2:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    srai a1, a0, 31
+; RV32I-NEXT:    srli a1, a1, 16
+; RV32I-NEXT:    add a1, a0, a1
+; RV32I-NEXT:    lui a2, 1048560
+; RV32I-NEXT:    and a1, a1, a2
+; RV32I-NEXT:    sub a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32IM-LABEL: srem_pow2_2:
+; RV32IM:       # %bb.0:
+; RV32IM-NEXT:    srai a1, a0, 31
+; RV32IM-NEXT:    srli a1, a1, 16
+; RV32IM-NEXT:    add a1, a0, a1
+; RV32IM-NEXT:    lui a2, 1048560
+; RV32IM-NEXT:    and a1, a1, a2
+; RV32IM-NEXT:    sub a0, a0, a1
+; RV32IM-NEXT:    ret
+;
+; RV64I-LABEL: srem_pow2_2:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    sext.w a1, a0
+; RV64I-NEXT:    srli a1, a1, 47
+; RV64I-NEXT:    lui a2, 16
+; RV64I-NEXT:    addiw a2, a2, -1
+; RV64I-NEXT:    and a1, a1, a2
+; RV64I-NEXT:    add a1, a0, a1
+; RV64I-NEXT:    lui a2, 1048560
+; RV64I-NEXT:    and a1, a1, a2
+; RV64I-NEXT:    subw a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64IM-LABEL: srem_pow2_2:
+; RV64IM:       # %bb.0:
+; RV64IM-NEXT:    sext.w a1, a0
+; RV64IM-NEXT:    srli a1, a1, 47
+; RV64IM-NEXT:    lui a2, 16
+; RV64IM-NEXT:    addiw a2, a2, -1
+; RV64IM-NEXT:    and a1, a1, a2
+; RV64IM-NEXT:    add a1, a0, a1
+; RV64IM-NEXT:    lui a2, 1048560
+; RV64IM-NEXT:    and a1, a1, a2
+; RV64IM-NEXT:    subw a0, a0, a1
+; RV64IM-NEXT:    ret
+  %1 = srem i32 %a, 65536
+  ret i32 %1
+}
+
 define i32 @srem_constant_lhs(i32 %a) nounwind {
 ; RV32I-LABEL: srem_constant_lhs:
 ; RV32I:       # %bb.0: