[PATCH] D105020: [SLP]Improve graph reordering.

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


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Comment at: llvm/test/Transforms/SLPVectorizer/AArch64/PR38339.ll:6-16
+; CHECK-NEXT:    [[T2:%.*]] = extractelement <2 x i16> [[X:%.*]], i32 0
+; CHECK-NEXT:    [[T3:%.*]] = extractelement <2 x i16> [[X]], i32 1
 ; CHECK-NEXT:    [[PTR0:%.*]] = getelementptr inbounds [4 x i16], [4 x i16]* undef, i16 0, i16 0
 ; CHECK-NEXT:    [[PTR1:%.*]] = getelementptr inbounds [4 x i16], [4 x i16]* undef, i16 0, i16 1
 ; CHECK-NEXT:    [[PTR2:%.*]] = getelementptr inbounds [4 x i16], [4 x i16]* undef, i16 0, i16 2
 ; CHECK-NEXT:    [[PTR3:%.*]] = getelementptr inbounds [4 x i16], [4 x i16]* undef, i16 0, i16 3
+; CHECK-NEXT:    store i16 [[T2]], i16* [[A:%.*]], align 2
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RKSimon wrote:
> ABataev wrote:
> > Need to adjust the cost for 4xi16 shuffle in AArch64 target.
> https://simd.godbolt.org/z/Pana3396f
> 
> @dmgreen Some very basic tests suggests the v4i16 shuffle cost should never be higher than 3 (which encouragingly matches what is already set for v4i32/v4f32) - do you agree?
> 
> ```
> // PermuteSingleSrc shuffle kinds.
> // TODO: handle vXi8/vXi16.
> { TTI::SK_PermuteSingleSrc, MVT::v2i32, 1 }, // mov.
> { TTI::SK_PermuteSingleSrc, MVT::v4i32, 3 }, // perfectshuffle worst case.
> { TTI::SK_PermuteSingleSrc, MVT::v2i64, 1 }, // mov.
> { TTI::SK_PermuteSingleSrc, MVT::v2f32, 1 }, // mov.
> { TTI::SK_PermuteSingleSrc, MVT::v4f32, 3 }, // perfectshuffle worst case.
> { TTI::SK_PermuteSingleSrc, MVT::v2f64, 1 }, // mov.
> ```
Yeah, I think that sounds right. GeneratePerfectShuffle applies to 4 element 64bit shuffles as well as 128bit shuffles, so the same 3 instruction worst case would apply.

I don't have a lot of tests that check SLP vectorization. Let me try some things and put a patch together if it looks sensible.


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https://reviews.llvm.org/D105020