[PATCH] D106053: [CodeGen] Remove pending AssertZext AssertSext in promoting FP_TO_INT

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

In D106053#2885525 <https://reviews.llvm.org/D106053#2885525>, @efriedma wrote:

> In D106053#2885502 <https://reviews.llvm.org/D106053#2885502>, @craig.topper wrote:
>
>> Ok that makes sense if the bitcast existed in IR. But this bitcast was created as part of type legalization and potentially spread poison to adjacent elements that didn't happen in the IR.

Oh, also, technically speaking, in fptoui-may-overflow.ll, the bitcast isn't getting created by type legalization; there's still a BUILD_VECTOR at that point.  The bitcast is getting built by DAGCombine.  From the debug dumps:

  Type-legalized selection DAG: %bb.0 'fptoui_shuffle:'
  SelectionDAG has 27 nodes:
    t0: ch = EntryToken
            t24: i32 = extract_vector_elt t19, Constant:i64<0>
          t25: i8 = truncate t24
            t27: i32 = extract_vector_elt t19, Constant:i64<1>
          t28: i8 = truncate t27
            t30: i32 = extract_vector_elt t19, Constant:i64<2>
          t31: i8 = truncate t30
            t33: i32 = extract_vector_elt t19, Constant:i64<3>
          t34: i8 = truncate t33
        t35: v16i8 = BUILD_VECTOR t25, t28, t31, t34, undef:i8, undef:i8, undef:i8, undef:i8, undef:i8, undef:i8, undef:i8, undef:i8, undef:i8, undef:i8, undef:i8, undef:i8
        t7: v16i8 = BUILD_VECTOR Constant:i8<0>, Constant:i8<0>, Constant:i8<0>, Constant:i8<0>, Constant:i8<0>, Constant:i8<0>, Constant:i8<0>, Constant:i8<0>, Constant:i8<0>, Constant:i8<0>, Constant:i8<0>, Constant:i8<0>, Constant:i8<0>, Constant:i8<0>, Constant:i8<0>, Constant:i8<0>
      t8: v16i8 = vector_shuffle<0,17,18,19,1,21,22,23,2,25,26,27,3,29,30,31> t35, t7
    t11: ch,glue = CopyToReg t0, Register:v16i8 $xmm0, t8
        t2: v4f32,ch = CopyFromReg t0, Register:v4f32 %0
      t17: v4i32 = fp_to_sint t2
    t19: v4i32 = AssertZext t17, ValueType:ch:i8
    t12: ch = X86ISD::RET_FLAG t11, TargetConstant:i32<0>, Register:v16i8 $xmm0, t11:1
  
  
  Optimized type-legalized selection DAG: %bb.0 'fptoui_shuffle:'
  SelectionDAG has 14 nodes:
    t0: ch = EntryToken
              t2: v4f32,ch = CopyFromReg t0, Register:v4f32 %0
            t17: v4i32 = fp_to_sint t2
          t19: v4i32 = AssertZext t17, ValueType:ch:i8
        t36: v16i8 = bitcast t19
        t7: v16i8 = BUILD_VECTOR Constant:i8<0>, Constant:i8<0>, Constant:i8<0>, Constant:i8<0>, Constant:i8<0>, Constant:i8<0>, Constant:i8<0>, Constant:i8<0>, Constant:i8<0>, Constant:i8<0>, Constant:i8<0>, Constant:i8<0>, Constant:i8<0>, Constant:i8<0>, Constant:i8<0>, Constant:i8<0>
      t48: v16i8 = vector_shuffle<0,17,18,19,4,21,22,23,8,25,26,27,12,29,30,31> t36, t7
    t11: ch,glue = CopyToReg t0, Register:v16i8 $xmm0, t48
    t12: ch = X86ISD::RET_FLAG t11, TargetConstant:i32<0>, Register:v16i8 $xmm0, t11:1


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106053/new/

https://reviews.llvm.org/D106053