[llvm] be8159b - [RISCV][RVV] Precommit a test case for D105684

[ShihPo Hung via llvm-commits]

Author: ShihPo Hung
Date: 2021-07-18T00:43:17+08:00
New Revision: be8159bfa56f89f72b33e089f7cdb2abc4f710f7

URL: https://github.com/llvm/llvm-project/commit/be8159bfa56f89f72b33e089f7cdb2abc4f710f7
DIFF: https://github.com/llvm/llvm-project/commit/be8159bfa56f89f72b33e089f7cdb2abc4f710f7.diff

LOG: [RISCV][RVV] Precommit a test case for D105684

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D105685

Added: 
    llvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir

Modified: 
    

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir b/llvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir
new file mode 100644
index 000000000000..6b19f65c6c79
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir
@@ -0,0 +1,23 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc %s -mtriple=riscv64 -mattr=+experimental-v -run-pass=simple-register-coalescing -o - | FileCheck %s
+---
+# Make sure that SrcReg & DstReg of PseudoVRGATHER are not coalesced
+name:            test_earlyclobber
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x10
+    ; CHECK-LABEL: name: test_earlyclobber
+    ; CHECK: liveins: $x10
+    ; CHECK: undef %2.sub_vrm2_0:vrn2m2 = PseudoVLE32_V_M2 $x10, 1, 5
+    ; CHECK: %2.sub_vrm2_1:vrn2m2 = PseudoVLE32_V_M2 $x10, 1, 5
+    ; CHECK: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 $x10, 1, 5
+    ; CHECK: early-clobber %2.sub_vrm2_0:vrn2m2 = PseudoVRGATHER_VI_M2 %2.sub_vrm2_0, 0, 1, 5, implicit $vl, implicit $vtype
+    ; CHECK: PseudoVSUXSEG2EI32_V_M2_M2 %2, $x10, [[PseudoVLE32_V_M2_]], 1, 5, implicit $vl, implicit $vtype
+    undef %0.sub_vrm2_0:vrn2m2 = PseudoVLE32_V_M2 $x10, 1, 5
+    %0.sub_vrm2_1:vrn2m2 = PseudoVLE32_V_M2 $x10, 1, 5
+    %1:vrm2 = PseudoVLE32_V_M2 $x10, 1, 5
+    undef early-clobber %2.sub_vrm2_0:vrn2m2 = PseudoVRGATHER_VI_M2 %0.sub_vrm2_0:vrn2m2, 0, 1, 5, implicit $vl, implicit $vtype
+    %2.sub_vrm2_1:vrn2m2 = COPY %0.sub_vrm2_1:vrn2m2
+    PseudoVSUXSEG2EI32_V_M2_M2 %2:vrn2m2, $x10, %1:vrm2, 1, 5, implicit $vl, implicit $vtype
+...