[PATCH] D106053: [CodeGen] Remove pending AssertZext AssertSext in promoting FP_TO_INT

Sat Jul 17 08:51:10 PDT 2021

jrtc27 added inline comments.

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Comment at: llvm/test/CodeGen/AArch64/arm64-convert-v4f64.ll:26-28
-; CHECK-DAG:  uzp1 v[[UZP0:[0-9]+]].4h, v[[XTN1]].4h, v[[XTN0]].4h
-; CHECK-DAG:  uzp1 v[[UZP1:[0-9]+]].4h, v[[XTN3]].4h, v[[XTN2]].4h
-; CHECK:      uzp1  v0.8b, v[[UZP1:[0-9]+]].8b, v[[UZP0:[0-9]+]].8b
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Did the instruction count actually go down or did you just delete the instructions that were no longer present but not add new ones? You've certainly lost the CHECK line for the final instruction that puts all the temporary values into the return register.

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Comment at: llvm/test/CodeGen/RISCV/rv64d-double-convert.ll:25
 ; RV64ID-NEXT:    fcvt.l.d a0, ft0, rtz
+; RV64ID-NEXT:    sext.w a0, a0
 ; RV64ID-NEXT:    ret
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All the RISC-V changes look like regressions to me unless I'm missing something...

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106053/new/

https://reviews.llvm.org/D106053