[llvm] f4ec30d - [RISCV] Make VLEN no greater than 65536

[Ben Shi via llvm-commits]

Author: jacquesguan
Date: 2021-07-17T12:47:46+08:00
New Revision: f4ec30d808a42812c754c45694aca982a06d6cfa

URL: https://github.com/llvm/llvm-project/commit/f4ec30d808a42812c754c45694aca982a06d6cfa
DIFF: https://github.com/llvm/llvm-project/commit/f4ec30d808a42812c754c45694aca982a06d6cfa.diff

LOG: [RISCV] Make VLEN no greater than 65536

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D106134

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVRegisterInfo.td
    llvm/lib/Target/RISCV/RISCVSubtarget.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index 320a7687a6c6..fde75206889c 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -285,8 +285,7 @@ def FPR64C : RegisterClass<"RISCV", [f64], 64, (add
 
 // Vector type mapping to LLVM types.
 //
-// Though the V extension allows that VLEN be as small as 8,
-// this approach assumes that VLEN>=64.
+// The V vector extension requires that VLEN >= 128 and <= 65536.
 // Additionally, the only supported ELEN values are 32 and 64,
 // thus `vscale` can be defined as VLEN/64,
 // allowing the same types with either ELEN value.

diff  --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
index c8764b5b4ffc..b19fdcb0082b 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -109,30 +109,32 @@ unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits() const {
   assert(hasStdExtV() && "Tried to get vector length without V support!");
   if (RVVVectorBitsMax == 0)
     return 0;
-  assert(RVVVectorBitsMax >= 128 && isPowerOf2_32(RVVVectorBitsMax) &&
-         "V extension requires vector length to be at least 128 and a power of "
-         "2!");
+  assert(RVVVectorBitsMax >= 128 && RVVVectorBitsMax <= 65536 &&
+         isPowerOf2_32(RVVVectorBitsMax) &&
+         "V extension requires vector length to be in the range of 128 to "
+         "65536 and a power of 2!");
   assert(RVVVectorBitsMax >= RVVVectorBitsMin &&
          "Minimum V extension vector length should not be larger than its "
          "maximum!");
   unsigned Max = std::max(RVVVectorBitsMin, RVVVectorBitsMax);
-  return PowerOf2Floor(Max < 128 ? 0 : Max);
+  return PowerOf2Floor((Max < 128 || Max > 65536) ? 0 : Max);
 }
 
 unsigned RISCVSubtarget::getMinRVVVectorSizeInBits() const {
   assert(hasStdExtV() &&
          "Tried to get vector length without V extension support!");
   assert((RVVVectorBitsMin == 0 ||
-          (RVVVectorBitsMin >= 128 && isPowerOf2_32(RVVVectorBitsMin))) &&
-         "V extension requires vector length to be at least 128 and a power of "
-         "2!");
+          (RVVVectorBitsMin >= 128 && RVVVectorBitsMax <= 65536 &&
+           isPowerOf2_32(RVVVectorBitsMin))) &&
+         "V extension requires vector length to be in the range of 128 to "
+         "65536 and a power of 2!");
   assert((RVVVectorBitsMax >= RVVVectorBitsMin || RVVVectorBitsMax == 0) &&
          "Minimum V extension vector length should not be larger than its "
          "maximum!");
   unsigned Min = RVVVectorBitsMin;
   if (RVVVectorBitsMax != 0)
     Min = std::min(RVVVectorBitsMin, RVVVectorBitsMax);
-  return PowerOf2Floor(Min < 128 ? 0 : Min);
+  return PowerOf2Floor((Min < 128 || Min > 65536) ? 0 : Min);
 }
 
 unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors() const {