[PATCH] D105953: [MachineVerifier] Diagnose invalid INSERT_SUBREGs

[Jon Roelofs via Phabricator via llvm-commits]

jroelofs updated this revision to Diff 359486.
jroelofs added a comment.

One of the two issues in the tests was easily fixable:
https://reviews.llvm.org/D106168

The other issue appears to be much trickier, as it stems from the ARM backend treating MPR regs as if they were ssub subregs. This causes a contradiction in sizes, since ssub's are 32 bits whereas MPR regs are fp16's.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105953/new/

https://reviews.llvm.org/D105953

Files:
  llvm/lib/CodeGen/MachineVerifier.cpp
  llvm/test/CodeGen/X86/domain-reassignment.mir
  llvm/test/MachineVerifier/test_insert_subreg.mir


Index: llvm/test/MachineVerifier/test_insert_subreg.mir
===================================================================
--- /dev/null
+++ llvm/test/MachineVerifier/test_insert_subreg.mir
@@ -0,0 +1,30 @@
+#RUN: not --crash llc -march=aarch64 -o - -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# REQUIRES: aarch64-registered-target
+
+---
+name:            test_insert_subreg
+legalized:       true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+body:             |
+  bb.0:
+    liveins: $s0, $h1
+
+    %0:fpr32 = COPY $s0
+
+    ; FIXME: we can't diagnose this case because the ARM backend treats fp16
+    ; values as being ssub regs, creating a contradiction in the sizes.
+    %1:fpr128 = IMPLICIT_DEF
+    %2:fpr128 = INSERT_SUBREG %1:fpr128, %0:fpr32, %subreg.hsub
+
+    ; CHECK: *** Bad machine code: INSERT_SUBREG expected inserted value to have equal or lesser size than the subreg it was inserted into ***
+    %3:fpr128 = IMPLICIT_DEF
+    %4:fpr128 = INSERT_SUBREG %3:fpr128, %0:fpr32, %subreg.dsub
+
+    ; CHECK-NOT: *** Bad machine code:
+    %7:fpr128 = IMPLICIT_DEF
+    %8:fpr128 = INSERT_SUBREG %7:fpr128, %0:fpr32, %subreg.ssub
+
+...
Index: llvm/test/CodeGen/X86/domain-reassignment.mir
===================================================================
--- llvm/test/CodeGen/X86/domain-reassignment.mir
+++ llvm/test/CodeGen/X86/domain-reassignment.mir
@@ -190,7 +190,7 @@
 
     %2 = PHI %1, %bb.2, %0, %bb.1
     %17 = IMPLICIT_DEF
-    %16 = INSERT_SUBREG %17, %2, 1
+    %16 = INSERT_SUBREG %17, %2, %subreg.sub_8bit_hi
     %18 = COPY %16
     %19 = COPY %6
     %21 = IMPLICIT_DEF
@@ -305,7 +305,7 @@
     %18 = ADD8rr %17, %14, implicit-def dead $eflags
 
     %8 = IMPLICIT_DEF
-    %9 = INSERT_SUBREG %8, %18, 1
+    %9 = INSERT_SUBREG %8, %18, %subreg.sub_8bit_hi
     %10 = COPY %9
     %11 = VMOVAPDZrrk %2, killed %10, %1
     VMOVAPDZmr %0, 1, $noreg, 0, $noreg, killed %11
@@ -423,7 +423,7 @@
     %17 = XOR16rr %16, %12, implicit-def dead $eflags
 
     %8 = IMPLICIT_DEF
-    %9 = INSERT_SUBREG %8, %17, 3
+    %9 = INSERT_SUBREG %8, %17, %subreg.sub_16bit
     %10 = COPY %9
     %11 = VMOVAPSZrrk %2, killed %10, %1
     VMOVAPSZmr %0, 1, $noreg, 0, $noreg, killed %11
Index: llvm/lib/CodeGen/MachineVerifier.cpp
===================================================================
--- llvm/lib/CodeGen/MachineVerifier.cpp
+++ llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1782,6 +1782,16 @@
 
     // TODO: verify we have properly encoded deopt arguments
   } break;
+  case TargetOpcode::INSERT_SUBREG: {
+    unsigned InsertedSize =
+        TRI->getRegSizeInBits(MI->getOperand(2).getReg(), *MRI);
+    unsigned SubRegSize = TRI->getSubRegIdxSize(MI->getOperand(3).getImm());
+    if (SubRegSize < InsertedSize) {
+      report("INSERT_SUBREG expected inserted value to have equal or lesser "
+             "size than the subreg it was inserted into", MI);
+      break;
+    }
+  } break;
   }
 }
 


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